2 * Copyright 2004 Freescale Semiconductor
3 * Jeff Brown (jeffrey@freescale.com)
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #if defined(CONFIG_OF_FLAT_TREE)
35 extern unsigned long get_board_sys_clk(ulong dummy);
38 static __inline__ unsigned long get_dbat3u (void)
41 asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
45 static __inline__ unsigned long get_dbat3l (void)
48 asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
52 static __inline__ unsigned long get_msr (void)
55 asm volatile("mfmsr %0" : "=r" (msr) :);
66 uint lcrr; /* local bus clock ratio register */
67 uint clkdiv; /* clock divider portion of lcrr */
69 puts("Freescale PowerPC\n");
81 case PVR_VER(PVR_86xx):
88 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
107 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
109 get_sys_info(&sysinfo);
112 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
113 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
114 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
116 #if defined(CFG_LBC_LCRR)
120 volatile immap_t *immap = (immap_t *)CFG_IMMR;
121 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
126 clkdiv = lcrr & 0x0f;
127 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
128 printf("LBC:%4lu MHz\n",
129 sysinfo.freqSystemBus / 1000000 / clkdiv);
131 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
135 if (get_l2cr() & 0x80000000)
138 printf("Disabled\n");
144 /* -------------------------------------------------------------------- */
147 soft_restart(unsigned long addr)
150 #ifndef CONFIG_MPC8641HPCN
152 /* SRR0 has system reset vector, SRR1 has default MSR value */
153 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
155 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
156 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
157 __asm__ __volatile__ ("mtspr 27, 4");
158 __asm__ __volatile__ ("rfi");
160 #else /* CONFIG_MPC8641HPCN */
161 out8(PIXIS_BASE+PIXIS_RST,0);
162 #endif /* !CONFIG_MPC8641HPCN */
163 while(1); /* not reached */
168 #ifdef CONFIG_MPC8641HPCN
170 int set_px_sysclk(ulong sysclk)
172 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
174 /* Per table 27, page 58 of MPC8641HPCN spec*/
226 printf("Unsupported SYSCLK frequency.\n");
230 vclkh = (sysclk_s << 5) | sysclk_r ;
232 out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
233 out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
235 out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
240 int set_px_mpxpll(ulong mpxpll)
257 printf("Unsupported MPXPLL ratio.\n");
261 tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
262 tmp = (tmp & 0xF0) | (val & 0x0F);
263 out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
268 int set_px_corepll(ulong corepll)
273 switch ((int)corepll) {
293 printf("Unsupported COREPLL ratio.\n");
297 tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
298 tmp = (tmp & 0xE0) | (val & 0x1F);
299 out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
304 void read_from_px_regs(int set)
307 tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0);
312 out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
315 void read_from_px_regs_altbank(int set)
318 tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1);
323 out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
326 void set_altbank(void)
329 tmp = in8(PIXIS_BASE+PIXIS_VBOOT);
331 out8(PIXIS_BASE+PIXIS_VBOOT,tmp);
338 tmp = in8(PIXIS_BASE+PIXIS_VCTL);
340 out8(PIXIS_BASE+PIXIS_VCTL,tmp);
341 tmp = in8(PIXIS_BASE+PIXIS_VCTL);
343 out8(PIXIS_BASE+PIXIS_VCTL,tmp);
346 void set_px_go_with_watchdog(void)
349 tmp = in8(PIXIS_BASE+PIXIS_VCTL);
351 out8(PIXIS_BASE+PIXIS_VCTL,tmp);
352 tmp = in8(PIXIS_BASE+PIXIS_VCTL);
354 out8(PIXIS_BASE+PIXIS_VCTL,tmp);
357 int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
360 tmp = in8(PIXIS_BASE+PIXIS_VCTL);
362 out8(PIXIS_BASE+PIXIS_VCTL,tmp);
363 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
364 tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
365 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
370 diswd, 1, 0, disable_watchdog,
371 "diswd - Disable watchdog timer \n",
375 /* This function takes the non-integral cpu:mpx pll ratio
376 * and converts it to an integer that can be used to assign
377 * FPGA register values.
378 * input: strptr i.e. argv[2]
381 ulong strfractoint(uchar *strptr)
383 int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0;
384 ulong intval =0, decval=0;
385 uchar intarr[3], decarr[3];
387 /* Assign the integer part to intarr[]
388 * If there is no decimal point i.e.
389 * if the ratio is an integral value
390 * simply create the intarr.
393 while(strptr[i] != 46)
398 break; /* Break from loop once the end of string is reached */
401 intarr[i] = strptr[i];
405 intarr_len = i; /* Assign length of integer part to intarr_len*/
406 intarr[i] = '\0'; /* */
410 mulconst=10; /* Currently needed only for single digit corepll ratios */
416 i++; /* Skipping the decimal point */
417 while ((strptr[i] > 47) && (strptr[i] < 58))
419 decarr[j] = strptr[i];
428 for(i=0; i<decarr_len;i++)
429 mulconst = mulconst*10;
430 decval = simple_strtoul(decarr,NULL,10);
433 intval = simple_strtoul(intarr,NULL,10);
434 intval = intval*mulconst;
436 retval = intval+decval;
443 #endif /* CONFIG_MPC8641HPCN */
446 /* no generic way to do board reset. simply call soft_reset. */
448 do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
454 #ifdef CFG_RESET_ADDRESS
455 addr = CFG_RESET_ADDRESS;
458 * note: when CFG_MONITOR_BASE points to a RAM address,
459 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
460 * address. Better pick an address known to be invalid on your
461 * system and assign it to CFG_RESET_ADDRESS.
463 addr = CFG_MONITOR_BASE - sizeof (ulong);
466 #ifndef CONFIG_MPC8641HPCN
468 /* flush and disable I/D cache */
469 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
470 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
471 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
472 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
473 __asm__ __volatile__ ("sync");
474 __asm__ __volatile__ ("mtspr 1008, 4");
475 __asm__ __volatile__ ("isync");
476 __asm__ __volatile__ ("sync");
477 __asm__ __volatile__ ("mtspr 1008, 5");
478 __asm__ __volatile__ ("isync");
479 __asm__ __volatile__ ("sync");
483 #else /* CONFIG_MPC8641HPCN */
488 case 'f': /* reset with frequency changed */
491 read_from_px_regs(0);
493 val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
495 corepll = strfractoint(argv[3]);
496 val = val + set_px_corepll(corepll);
497 val = val + set_px_mpxpll(simple_strtoul(argv[4],
500 printf("Setting registers VCFGEN0 and VCTL\n");
501 read_from_px_regs(1);
502 printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
507 while (1); /* Not reached */
510 if (argv[2][1] == 'f') {
511 read_from_px_regs(0);
512 read_from_px_regs_altbank(0);
513 /* reset with frequency changed */
514 val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
516 corepll = strfractoint(argv[4]);
517 val = val + set_px_corepll(corepll);
518 val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
520 printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
522 read_from_px_regs(1);
523 read_from_px_regs_altbank(1);
524 printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
525 set_px_go_with_watchdog();
529 while(1); /* Not reached */
530 } else if(argv[2][1] == 'd'){
531 /* Reset from next bank without changing frequencies but with watchdog timer enabled */
532 read_from_px_regs(0);
533 read_from_px_regs_altbank(0);
534 printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
536 read_from_px_regs_altbank(1);
537 printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
538 set_px_go_with_watchdog();
539 while(1); /* Not reached */
541 /* Reset from next bank without changing frequency and without watchdog timer enabled */
542 read_from_px_regs(0);
543 read_from_px_regs_altbank(0);
546 printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
548 read_from_px_regs_altbank(1);
549 printf("Resetting board to boot from the other bank....\n");
558 printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
559 printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
560 printf("For example: reset cf 40 2.5 10\n");
561 printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
564 out8(PIXIS_BASE+PIXIS_RST,0);
566 #endif /* !CONFIG_MPC8641HPCN */
568 while(1); /* not reached */
573 * Get timebase clock frequency
575 unsigned long get_tbclk(void)
579 get_sys_info(&sys_info);
580 return (sys_info.freqSystemBus + 3L) / 4L;
584 #if defined(CONFIG_WATCHDOG)
589 #endif /* CONFIG_WATCHDOG */
592 #if defined(CONFIG_DDR_ECC)
595 volatile immap_t *immap = (immap_t *)CFG_IMMR;
596 volatile ccsr_dma_t *dma = &immap->im_dma;
598 dma->satr0 = 0x00040000;
599 dma->datr0 = 0x00040000;
606 volatile immap_t *immap = (immap_t *)CFG_IMMR;
607 volatile ccsr_dma_t *dma = &immap->im_dma;
608 volatile uint status = dma->sr0;
610 /* While the channel is busy, spin */
611 while((status & 4) == 4) {
616 printf ("DMA Error: status = %x\n", status);
621 int dma_xfer(void *dest, uint count, void *src)
623 volatile immap_t *immap = (immap_t *)CFG_IMMR;
624 volatile ccsr_dma_t *dma = &immap->im_dma;
626 dma->dar0 = (uint) dest;
627 dma->sar0 = (uint) src;
629 dma->mr0 = 0xf000004;
631 dma->mr0 = 0xf000005;
636 #endif /* CONFIG_DDR_ECC */
639 #ifdef CONFIG_OF_FLAT_TREE
640 void ft_cpu_setup(void *blob, bd_t *bd)
646 clock = bd->bi_busfreq;
647 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
649 *p = cpu_to_be32(clock);
651 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
653 *p = cpu_to_be32(clock);
655 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
657 *p = cpu_to_be32(clock);
659 #if defined(CONFIG_MPC86XX_TSEC1)
660 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
661 memcpy(p, bd->bi_enetaddr, 6);
664 #if defined(CONFIG_MPC86XX_TSEC2)
665 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
666 memcpy(p, bd->bi_enet1addr, 6);
669 #if defined(CONFIG_MPC86XX_TSEC3)
670 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len);
671 memcpy(p, bd->bi_enet2addr, 6);
674 #if defined(CONFIG_MPC86XX_TSEC4)
675 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len);
676 memcpy(p, bd->bi_enet3addr, 6);