2 * Copyright 2004 Freescale Semiconductor
3 * Jeff Brown (jeffrey@freescale.com)
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #if defined(CONFIG_OF_FLAT_TREE)
35 #include "../board/mpc8641hpcn/pixis.h"
38 static __inline__ unsigned long get_dbat3u (void)
41 asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
45 static __inline__ unsigned long get_dbat3l (void)
48 asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
52 static __inline__ unsigned long get_msr (void)
55 asm volatile("mfmsr %0" : "=r" (msr) :);
66 uint lcrr; /* local bus clock ratio register */
67 uint clkdiv; /* clock divider portion of lcrr */
69 puts("Freescale PowerPC\n");
81 case PVR_VER(PVR_86xx):
88 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
107 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
109 get_sys_info(&sysinfo);
112 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
113 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
114 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
116 #if defined(CFG_LBC_LCRR)
120 volatile immap_t *immap = (immap_t *)CFG_IMMR;
121 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
126 clkdiv = lcrr & 0x0f;
127 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
128 printf("LBC:%4lu MHz\n",
129 sysinfo.freqSystemBus / 1000000 / clkdiv);
131 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
135 if (get_l2cr() & 0x80000000)
138 printf("Disabled\n");
144 /* -------------------------------------------------------------------- */
147 soft_restart(unsigned long addr)
150 #ifndef CONFIG_MPC8641HPCN
152 /* SRR0 has system reset vector, SRR1 has default MSR value */
153 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
155 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
156 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
157 __asm__ __volatile__ ("mtspr 27, 4");
158 __asm__ __volatile__ ("rfi");
160 #else /* CONFIG_MPC8641HPCN */
161 out8(PIXIS_BASE+PIXIS_RST,0);
162 #endif /* !CONFIG_MPC8641HPCN */
163 while(1); /* not reached */
168 * No generic way to do board reset. Simply call soft_reset.
171 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
177 #ifdef CFG_RESET_ADDRESS
178 addr = CFG_RESET_ADDRESS;
181 * note: when CFG_MONITOR_BASE points to a RAM address,
182 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
183 * address. Better pick an address known to be invalid on your
184 * system and assign it to CFG_RESET_ADDRESS.
186 addr = CFG_MONITOR_BASE - sizeof (ulong);
189 #ifndef CONFIG_MPC8641HPCN
191 /* flush and disable I/D cache */
192 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
193 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
194 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
195 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
196 __asm__ __volatile__ ("sync");
197 __asm__ __volatile__ ("mtspr 1008, 4");
198 __asm__ __volatile__ ("isync");
199 __asm__ __volatile__ ("sync");
200 __asm__ __volatile__ ("mtspr 1008, 5");
201 __asm__ __volatile__ ("isync");
202 __asm__ __volatile__ ("sync");
206 #else /* CONFIG_MPC8641HPCN */
211 case 'f': /* reset with frequency changed */
214 read_from_px_regs(0);
216 val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
218 corepll = strfractoint(argv[3]);
219 val = val + set_px_corepll(corepll);
220 val = val + set_px_mpxpll(simple_strtoul(argv[4],
223 printf("Setting registers VCFGEN0 and VCTL\n");
224 read_from_px_regs(1);
225 printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
230 while (1); /* Not reached */
233 if (argv[2][1] == 'f') {
234 read_from_px_regs(0);
235 read_from_px_regs_altbank(0);
236 /* reset with frequency changed */
237 val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
239 corepll = strfractoint(argv[4]);
240 val = val + set_px_corepll(corepll);
241 val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
243 printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
245 read_from_px_regs(1);
246 read_from_px_regs_altbank(1);
247 printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
248 set_px_go_with_watchdog();
252 while(1); /* Not reached */
253 } else if(argv[2][1] == 'd'){
254 /* Reset from next bank without changing frequencies but with watchdog timer enabled */
255 read_from_px_regs(0);
256 read_from_px_regs_altbank(0);
257 printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
259 read_from_px_regs_altbank(1);
260 printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
261 set_px_go_with_watchdog();
262 while(1); /* Not reached */
264 /* Reset from next bank without changing frequency and without watchdog timer enabled */
265 read_from_px_regs(0);
266 read_from_px_regs_altbank(0);
269 printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
271 read_from_px_regs_altbank(1);
272 printf("Resetting board to boot from the other bank....\n");
281 printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
282 printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
283 printf("For example: reset cf 40 2.5 10\n");
284 printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
287 out8(PIXIS_BASE+PIXIS_RST,0);
289 #endif /* !CONFIG_MPC8641HPCN */
291 while(1); /* not reached */
296 * Get timebase clock frequency
298 unsigned long get_tbclk(void)
302 get_sys_info(&sys_info);
303 return (sys_info.freqSystemBus + 3L) / 4L;
307 #if defined(CONFIG_WATCHDOG)
312 #endif /* CONFIG_WATCHDOG */
315 #if defined(CONFIG_DDR_ECC)
318 volatile immap_t *immap = (immap_t *)CFG_IMMR;
319 volatile ccsr_dma_t *dma = &immap->im_dma;
321 dma->satr0 = 0x00040000;
322 dma->datr0 = 0x00040000;
328 volatile immap_t *immap = (immap_t *)CFG_IMMR;
329 volatile ccsr_dma_t *dma = &immap->im_dma;
330 volatile uint status = dma->sr0;
332 /* While the channel is busy, spin */
333 while((status & 4) == 4) {
338 printf ("DMA Error: status = %x\n", status);
343 int dma_xfer(void *dest, uint count, void *src)
345 volatile immap_t *immap = (immap_t *)CFG_IMMR;
346 volatile ccsr_dma_t *dma = &immap->im_dma;
348 dma->dar0 = (uint) dest;
349 dma->sar0 = (uint) src;
351 dma->mr0 = 0xf000004;
353 dma->mr0 = 0xf000005;
358 #endif /* CONFIG_DDR_ECC */
361 #ifdef CONFIG_OF_FLAT_TREE
362 void ft_cpu_setup(void *blob, bd_t *bd)
368 clock = bd->bi_busfreq;
369 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
371 *p = cpu_to_be32(clock);
373 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
375 *p = cpu_to_be32(clock);
377 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
379 *p = cpu_to_be32(clock);
381 #if defined(CONFIG_MPC86XX_TSEC1)
382 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
383 memcpy(p, bd->bi_enetaddr, 6);
386 #if defined(CONFIG_MPC86XX_TSEC2)
387 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
388 memcpy(p, bd->bi_enet1addr, 6);
391 #if defined(CONFIG_MPC86XX_TSEC3)
392 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len);
393 memcpy(p, bd->bi_enet2addr, 6);
396 #if defined(CONFIG_MPC86XX_TSEC4)
397 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len);
398 memcpy(p, bd->bi_enet3addr, 6);