2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
32 #include <asm/fsl_law.h>
42 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
43 volatile ccsr_gur_t *gur = &immap->im_gur;
45 puts("Freescale PowerPC\n");
56 case PVR_VER(PVR_86xx):
58 uint msscr0 = mfspr(MSSCR0);
59 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
60 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
61 puts("\n Core1Translation Enabled");
62 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
69 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
72 ver = SVR_SOC_VER(svr);
79 if (SVR_SUBVER(svr) == 1) {
92 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
94 get_sys_info(&sysinfo);
97 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
98 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
99 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
101 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
102 printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
104 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
105 sysinfo.freqLocalBus);
109 if (get_l2cr() & 0x80000000)
119 soft_restart(unsigned long addr)
121 #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
124 * SRR0 has system reset vector, SRR1 has default MSR value
125 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
128 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
129 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
130 __asm__ __volatile__ ("mtspr 27, 4");
131 __asm__ __volatile__ ("rfi");
133 #else /* CONFIG_MPC8641HPCN */
135 out8(PIXIS_BASE + PIXIS_RST, 0);
137 #endif /* !CONFIG_MPC8641HPCN */
139 while (1) ; /* not reached */
144 * No generic way to do board reset. Simply call soft_reset.
147 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
149 #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
151 #ifdef CONFIG_SYS_RESET_ADDRESS
152 ulong addr = CONFIG_SYS_RESET_ADDRESS;
155 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
156 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
157 * address. Better pick an address known to be invalid on your
158 * system and assign it to CONFIG_SYS_RESET_ADDRESS.
160 ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
163 /* flush and disable I/D cache */
164 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
165 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
166 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
167 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
168 __asm__ __volatile__ ("sync");
169 __asm__ __volatile__ ("mtspr 1008, 4");
170 __asm__ __volatile__ ("isync");
171 __asm__ __volatile__ ("sync");
172 __asm__ __volatile__ ("mtspr 1008, 5");
173 __asm__ __volatile__ ("isync");
174 __asm__ __volatile__ ("sync");
178 #else /* CONFIG_MPC8641HPCN */
180 out8(PIXIS_BASE + PIXIS_RST, 0);
182 #endif /* !CONFIG_MPC8641HPCN */
184 while (1) ; /* not reached */
189 * Get timebase clock frequency
196 get_sys_info(&sys_info);
197 return (sys_info.freqSystemBus + 3L) / 4L;
201 #if defined(CONFIG_WATCHDOG)
205 #if defined(CONFIG_MPC8610)
207 * This actually feed the hard enabled watchdog.
209 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
210 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
211 volatile ccsr_gur_t *gur = &immap->im_gur;
212 u32 tmp = gur->pordevsr;
220 #endif /* CONFIG_WATCHDOG */
223 #if defined(CONFIG_DDR_ECC)
227 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
228 volatile ccsr_dma_t *dma = &immap->im_dma;
230 dma->satr0 = 0x00040000;
231 dma->datr0 = 0x00040000;
238 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
239 volatile ccsr_dma_t *dma = &immap->im_dma;
240 volatile uint status = dma->sr0;
242 /* While the channel is busy, spin */
243 while ((status & 4) == 4) {
248 printf("DMA Error: status = %x\n", status);
254 dma_xfer(void *dest, uint count, void *src)
256 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
257 volatile ccsr_dma_t *dma = &immap->im_dma;
259 dma->dar0 = (uint) dest;
260 dma->sar0 = (uint) src;
262 dma->mr0 = 0xf000004;
264 dma->mr0 = 0xf000005;
269 #endif /* CONFIG_DDR_ECC */
273 * Print out the state of various machine registers.
274 * Currently prints out LAWs, BR0/OR0, and BATs
276 void mpc86xx_reginfo(void)
278 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
279 ccsr_lbc_t *lbc = &immap->im_lbc;
284 printf ("Local Bus Controller Registers\n"
285 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
286 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
287 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
288 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
289 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
290 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
291 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
292 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
297 * Initializes on-chip ethernet controllers.
298 * to override, implement board_eth_init()
300 int cpu_eth_init(bd_t *bis)
302 #if defined(CONFIG_TSEC_ENET)
303 tsec_standard_init(bis);