2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
32 #include <asm/fsl_law.h>
36 * Default board reset function
43 void board_reset(void) __attribute((weak, alias("__board_reset")));
53 char buf1[32], buf2[32];
54 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
55 volatile ccsr_gur_t *gur = &immap->im_gur;
56 uint msscr0 = mfspr(MSSCR0);
59 ver = SVR_SOC_VER(svr);
79 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
83 ver = PVR_E600_VER(pvr);
84 major = PVR_E600_MAJ(pvr);
85 minor = PVR_E600_MIN(pvr);
87 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
88 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
89 puts("\n Core1Translation Enabled");
90 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
92 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
94 get_sys_info(&sysinfo);
96 puts("Clock Configuration:\n");
97 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
98 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
99 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
100 strmhz(buf1, sysinfo.freqSystemBus / 2),
101 strmhz(buf2, sysinfo.freqSystemBus));
103 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
104 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
106 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
107 sysinfo.freqLocalBus);
110 puts("L1: D-cache 32 KB enabled\n");
111 puts(" I-cache 32 KB enabled\n");
114 if (get_l2cr() & 0x80000000) {
115 #if defined(CONFIG_MPC8610)
117 #elif defined(CONFIG_MPC8641)
120 puts(" KB enabled\n");
130 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
133 volatile ccsr_gur_t *gur = &immap->im_gur;
135 /* Attempt board-specific reset */
138 /* Next try asserting HRESET_REQ */
139 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
147 * Get timebase clock frequency
154 get_sys_info(&sys_info);
155 return (sys_info.freqSystemBus + 3L) / 4L;
159 #if defined(CONFIG_WATCHDOG)
163 #if defined(CONFIG_MPC8610)
165 * This actually feed the hard enabled watchdog.
167 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
168 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
169 volatile ccsr_gur_t *gur = &immap->im_gur;
170 u32 tmp = gur->pordevsr;
178 #endif /* CONFIG_WATCHDOG */
181 #if defined(CONFIG_DDR_ECC)
185 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
186 volatile ccsr_dma_t *dma = &immap->im_dma;
188 dma->satr0 = 0x00040000;
189 dma->datr0 = 0x00040000;
196 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
197 volatile ccsr_dma_t *dma = &immap->im_dma;
198 volatile uint status = dma->sr0;
200 /* While the channel is busy, spin */
201 while ((status & 4) == 4) {
206 printf("DMA Error: status = %x\n", status);
212 dma_xfer(void *dest, uint count, void *src)
214 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
215 volatile ccsr_dma_t *dma = &immap->im_dma;
217 dma->dar0 = (uint) dest;
218 dma->sar0 = (uint) src;
220 dma->mr0 = 0xf000004;
222 dma->mr0 = 0xf000005;
227 #endif /* CONFIG_DDR_ECC */
231 * Print out the state of various machine registers.
232 * Currently prints out LAWs, BR0/OR0, and BATs
234 void mpc86xx_reginfo(void)
236 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
237 ccsr_lbc_t *lbc = &immap->im_lbc;
242 printf ("Local Bus Controller Registers\n"
243 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
244 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
245 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
246 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
247 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
248 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
249 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
250 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
255 * Initializes on-chip ethernet controllers.
256 * to override, implement board_eth_init()
258 int cpu_eth_init(bd_t *bis)
260 #if defined(CONFIG_TSEC_ENET)
261 tsec_standard_init(bis);