4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
24 #define TSEC_SIZE 0x01000
26 #define MAC_ADDR_LEN 6
28 /* #define TSEC_TIMEOUT 1000000 */
29 #define TSEC_TIMEOUT 1000
30 #define TOUT_LOOP 1000000
32 /* MAC register bits */
33 #define MACCFG1_SOFT_RESET 0x80000000
34 #define MACCFG1_RESET_RX_MC 0x00080000
35 #define MACCFG1_RESET_TX_MC 0x00040000
36 #define MACCFG1_RESET_RX_FUN 0x00020000
37 #define MACCFG1_RESET_TX_FUN 0x00010000
38 #define MACCFG1_LOOPBACK 0x00000100
39 #define MACCFG1_RX_FLOW 0x00000020
40 #define MACCFG1_TX_FLOW 0x00000010
41 #define MACCFG1_SYNCD_RX_EN 0x00000008
42 #define MACCFG1_RX_EN 0x00000004
43 #define MACCFG1_SYNCD_TX_EN 0x00000002
44 #define MACCFG1_TX_EN 0x00000001
46 #define MACCFG2_INIT_SETTINGS 0x00007205
47 #define MACCFG2_FULL_DUPLEX 0x00000001
48 #define MACCFG2_IF 0x00000300
49 #define MACCFG2_GMII 0x00000200
50 #define MACCFG2_MII 0x00000100
52 #define ECNTRL_INIT_SETTINGS 0x00001000
53 #define ECNTRL_TBI_MODE 0x00000020
58 #define TBIPA_VALUE 0x1f
59 #define MIIMCFG_INIT_VALUE 0x00000003
60 #define MIIMCFG_RESET 0x80000000
62 #define MIIMIND_BUSY 0x00000001
63 #define MIIMIND_NOTVALID 0x00000004
65 #define MIIM_CONTROL 0x00
66 #define MIIM_CONTROL_RESET 0x00009140
67 #define MIIM_CONTROL_INIT 0x00001140
68 #define MIIM_ANEN 0x00001000
71 #define MIIM_CR_RST 0x00008000
72 #define MIIM_CR_INIT 0x00001000
74 #define MIIM_STATUS 0x1
75 #define MIIM_STATUS_AN_DONE 0x00000020
76 #define MIIM_STATUS_LINK 0x0004
78 #define MIIM_PHYIR1 0x2
79 #define MIIM_PHYIR2 0x3
82 #define MIIM_ANAR_INIT 0x1e1
84 #define MIIM_TBI_ANLPBPA 0x5
85 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
86 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
88 #define MIIM_TBI_ANEX 0x6
89 #define MIIM_TBI_ANEX_NP 0x00000004
90 #define MIIM_TBI_ANEX_PRX 0x00000002
92 #define MIIM_GBIT_CONTROL 0x9
93 #define MIIM_GBIT_CONTROL_INIT 0xe00
95 /* Cicada Auxiliary Control/Status Register */
96 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
97 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
98 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
99 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
100 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
101 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
103 /* Cicada Extended Control Register 1 */
104 #define MIIM_CIS8201_EXT_CON1 0x17
105 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
107 /* Cicada 8204 Extended PHY Control Register 1 */
108 #define MIIM_CIS8204_EPHY_CON 0x17
109 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
111 /* Cicada 8204 Serial LED Control Register */
112 #define MIIM_CIS8204_SLED_CON 0x1b
113 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
115 #define MIIM_GBIT_CON 0x09
116 #define MIIM_GBIT_CON_ADVERT 0x0e00
118 /* 88E1011 PHY Status Register */
119 #define MIIM_88E1011_PHY_STATUS 0x11
120 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
121 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
122 #define MIIM_88E1011_PHYSTAT_100 0x4000
123 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
124 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
125 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
127 /* DM9161 Control register values */
128 #define MIIM_DM9161_CR_STOP 0x0400
129 #define MIIM_DM9161_CR_RSTAN 0x1200
131 #define MIIM_DM9161_SCR 0x10
132 #define MIIM_DM9161_SCR_INIT 0x0610
134 /* DM9161 Specified Configuration and Status Register */
135 #define MIIM_DM9161_SCSR 0x11
136 #define MIIM_DM9161_SCSR_100F 0x8000
137 #define MIIM_DM9161_SCSR_100H 0x4000
138 #define MIIM_DM9161_SCSR_10F 0x2000
139 #define MIIM_DM9161_SCSR_10H 0x1000
141 /* DM9161 10BT Configuration/Status */
142 #define MIIM_DM9161_10BTCSR 0x12
143 #define MIIM_DM9161_10BTCSR_INIT 0x7800
145 #define MIIM_READ_COMMAND 0x00000001
147 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
149 #define MINFLR_INIT_SETTINGS 0x00000040
151 #define DMACTRL_INIT_SETTINGS 0x000000c3
152 #define DMACTRL_GRS 0x00000010
153 #define DMACTRL_GTS 0x00000008
155 #define TSTAT_CLEAR_THALT 0x80000000
156 #define RSTAT_CLEAR_RHALT 0x00800000
159 #define IEVENT_INIT_CLEAR 0xffffffff
160 #define IEVENT_BABR 0x80000000
161 #define IEVENT_RXC 0x40000000
162 #define IEVENT_BSY 0x20000000
163 #define IEVENT_EBERR 0x10000000
164 #define IEVENT_MSRO 0x04000000
165 #define IEVENT_GTSC 0x02000000
166 #define IEVENT_BABT 0x01000000
167 #define IEVENT_TXC 0x00800000
168 #define IEVENT_TXE 0x00400000
169 #define IEVENT_TXB 0x00200000
170 #define IEVENT_TXF 0x00100000
171 #define IEVENT_IE 0x00080000
172 #define IEVENT_LC 0x00040000
173 #define IEVENT_CRL 0x00020000
174 #define IEVENT_XFUN 0x00010000
175 #define IEVENT_RXB0 0x00008000
176 #define IEVENT_GRSC 0x00000100
177 #define IEVENT_RXF0 0x00000080
179 #define IMASK_INIT_CLEAR 0x00000000
180 #define IMASK_TXEEN 0x00400000
181 #define IMASK_TXBEN 0x00200000
182 #define IMASK_TXFEN 0x00100000
183 #define IMASK_RXFEN0 0x00000080
186 /* Default Attribute fields */
187 #define ATTR_INIT_SETTINGS 0x000000c0
188 #define ATTRELI_INIT_SETTINGS 0x00000000
191 /* TxBD status field bits */
192 #define TXBD_READY 0x8000
193 #define TXBD_PADCRC 0x4000
194 #define TXBD_WRAP 0x2000
195 #define TXBD_INTERRUPT 0x1000
196 #define TXBD_LAST 0x0800
197 #define TXBD_CRC 0x0400
198 #define TXBD_DEF 0x0200
199 #define TXBD_HUGEFRAME 0x0080
200 #define TXBD_LATECOLLISION 0x0080
201 #define TXBD_RETRYLIMIT 0x0040
202 #define TXBD_RETRYCOUNTMASK 0x003c
203 #define TXBD_UNDERRUN 0x0002
204 #define TXBD_STATS 0x03ff
206 /* RxBD status field bits */
207 #define RXBD_EMPTY 0x8000
208 #define RXBD_RO1 0x4000
209 #define RXBD_WRAP 0x2000
210 #define RXBD_INTERRUPT 0x1000
211 #define RXBD_LAST 0x0800
212 #define RXBD_FIRST 0x0400
213 #define RXBD_MISS 0x0100
214 #define RXBD_BROADCAST 0x0080
215 #define RXBD_MULTICAST 0x0040
216 #define RXBD_LARGE 0x0020
217 #define RXBD_NONOCTET 0x0010
218 #define RXBD_SHORT 0x0008
219 #define RXBD_CRCERR 0x0004
220 #define RXBD_OVERRUN 0x0002
221 #define RXBD_TRUNCATED 0x0001
222 #define RXBD_STATS 0x003f
226 ushort status; /* Status Fields */
227 ushort length; /* Buffer length */
228 uint bufPtr; /* Buffer Pointer */
233 ushort status; /* Status Fields */
234 ushort length; /* Buffer Length */
235 uint bufPtr; /* Buffer Pointer */
238 typedef struct rmon_mib
240 /* Transmit and Receive Counters */
241 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
242 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
243 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
244 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
245 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
246 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
247 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
248 /* Receive Counters */
249 uint rbyt; /* Receive Byte Counter */
250 uint rpkt; /* Receive Packet Counter */
251 uint rfcs; /* Receive FCS Error Counter */
252 uint rmca; /* Receive Multicast Packet (Counter) */
253 uint rbca; /* Receive Broadcast Packet */
254 uint rxcf; /* Receive Control Frame Packet */
255 uint rxpf; /* Receive Pause Frame Packet */
256 uint rxuo; /* Receive Unknown OP Code */
257 uint raln; /* Receive Alignment Error */
258 uint rflr; /* Receive Frame Length Error */
259 uint rcde; /* Receive Code Error */
260 uint rcse; /* Receive Carrier Sense Error */
261 uint rund; /* Receive Undersize Packet */
262 uint rovr; /* Receive Oversize Packet */
263 uint rfrg; /* Receive Fragments */
264 uint rjbr; /* Receive Jabber */
265 uint rdrp; /* Receive Drop */
266 /* Transmit Counters */
267 uint tbyt; /* Transmit Byte Counter */
268 uint tpkt; /* Transmit Packet */
269 uint tmca; /* Transmit Multicast Packet */
270 uint tbca; /* Transmit Broadcast Packet */
271 uint txpf; /* Transmit Pause Control Frame */
272 uint tdfr; /* Transmit Deferral Packet */
273 uint tedf; /* Transmit Excessive Deferral Packet */
274 uint tscl; /* Transmit Single Collision Packet */
276 uint tmcl; /* Transmit Multiple Collision Packet */
277 uint tlcl; /* Transmit Late Collision Packet */
278 uint txcl; /* Transmit Excessive Collision Packet */
279 uint tncl; /* Transmit Total Collision */
283 uint tdrp; /* Transmit Drop Frame */
284 uint tjbr; /* Transmit Jabber Frame */
285 uint tfcs; /* Transmit FCS Error */
286 uint txcf; /* Transmit Control Frame */
287 uint tovr; /* Transmit Oversize Frame */
288 uint tund; /* Transmit Undersize Frame */
289 uint tfrg; /* Transmit Fragments Frame */
290 /* General Registers */
291 uint car1; /* Carry Register One */
292 uint car2; /* Carry Register Two */
293 uint cam1; /* Carry Register One Mask */
294 uint cam2; /* Carry Register Two Mask */
297 typedef struct tsec_hash_regs
299 uint iaddr0; /* Individual Address Register 0 */
300 uint iaddr1; /* Individual Address Register 1 */
301 uint iaddr2; /* Individual Address Register 2 */
302 uint iaddr3; /* Individual Address Register 3 */
303 uint iaddr4; /* Individual Address Register 4 */
304 uint iaddr5; /* Individual Address Register 5 */
305 uint iaddr6; /* Individual Address Register 6 */
306 uint iaddr7; /* Individual Address Register 7 */
308 uint gaddr0; /* Group Address Register 0 */
309 uint gaddr1; /* Group Address Register 1 */
310 uint gaddr2; /* Group Address Register 2 */
311 uint gaddr3; /* Group Address Register 3 */
312 uint gaddr4; /* Group Address Register 4 */
313 uint gaddr5; /* Group Address Register 5 */
314 uint gaddr6; /* Group Address Register 6 */
315 uint gaddr7; /* Group Address Register 7 */
321 /* General Control and Status Registers (0x2_n000) */
324 uint ievent; /* Interrupt Event */
325 uint imask; /* Interrupt Mask */
326 uint edis; /* Error Disabled */
328 uint ecntrl; /* Ethernet Control */
329 uint minflr; /* Minimum Frame Length */
330 uint ptv; /* Pause Time Value */
331 uint dmactrl; /* DMA Control */
332 uint tbipa; /* TBI PHY Address */
337 /* Transmit Control and Status Registers (0x2_n100) */
338 uint tctrl; /* Transmit Control */
339 uint tstat; /* Transmit Status */
341 uint tbdlen; /* Tx BD Data Length */
343 uint ctbptr; /* Current TxBD Pointer */
345 uint tbptr; /* TxBD Pointer */
349 uint tbase; /* TxBD Base Address */
351 uint ostbd; /* Out of Sequence TxBD */
352 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
355 /* Receive Control and Status Registers (0x2_n300) */
356 uint rctrl; /* Receive Control */
357 uint rstat; /* Receive Status */
359 uint rbdlen; /* RxBD Data Length */
362 uint crbptr; /* Current Receive Buffer Pointer */
364 uint mrblr; /* Maximum Receive Buffer Length */
366 uint rbptr; /* RxBD Pointer */
370 uint rbase; /* RxBD Base Address */
373 /* MAC Registers (0x2_n500) */
374 uint maccfg1; /* MAC Configuration #1 */
375 uint maccfg2; /* MAC Configuration #2 */
376 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
377 uint hafdup; /* Half-duplex */
378 uint maxfrm; /* Maximum Frame */
384 uint miimcfg; /* MII Management: Configuration */
385 uint miimcom; /* MII Management: Command */
386 uint miimadd; /* MII Management: Address */
387 uint miimcon; /* MII Management: Control */
388 uint miimstat; /* MII Management: Status */
389 uint miimind; /* MII Management: Indicators */
393 uint ifstat; /* Interface Status */
394 uint macstnaddr1; /* Station Address, part 1 */
395 uint macstnaddr2; /* Station Address, part 2 */
401 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
405 /* Hash Function Registers (0x2_n800) */
410 /* Pattern Registers (0x2_nb00) */
412 uint attr; /* Default Attribute Register */
413 uint attreli; /* Default Attribute Extract Length and Index */
415 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
419 struct tsec_private {
420 volatile tsec_t *regs;
421 volatile tsec_t *phyregs;
422 struct phy_info *phyinfo;
432 * struct phy_cmd: A command for reading or writing a PHY register
434 * mii_reg: The register to read or write
436 * mii_data: For writes, the value to put in the register.
437 * A value of -1 indicates this is a read.
439 * funct: A function pointer which is invoked for each command.
440 * For reads, this function will be passed the value read
441 * from the PHY, and process it.
442 * For writes, the result of this function will be written
443 * to the PHY register
448 uint (*funct) (uint mii_reg, struct tsec_private* priv);
451 /* struct phy_info: a structure which defines attributes for a PHY
453 * id will contain a number which represents the PHY. During
454 * startup, the driver will poll the PHY to find out what its
455 * UID--as defined by registers 2 and 3--is. The 32-bit result
456 * gotten from the PHY will be shifted right by "shift" bits to
457 * discard any bits which may change based on revision numbers
458 * unimportant to functionality
460 * The struct phy_cmd entries represent pointers to an arrays of
461 * commands which tell the driver what to do to the PHY.
467 /* Called to configure the PHY, and modify the controller
468 * based on the results */
469 struct phy_cmd *config;
471 /* Called when starting up the controller */
472 struct phy_cmd *startup;
474 /* Called when bringing down the controller */
475 struct phy_cmd *shutdown;
478 #endif /* __TSEC_H */