3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
11 * maintained by Jon Loeliger (loeliger@freescale.com)
23 #if defined(CONFIG_TSEC_ENET)
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 struct tsec_info_struct {
39 unsigned int phyregidx;
43 /* The tsec_info structure contains 3 values which the
44 * driver uses to determine how to operate a given ethernet
45 * device. For now, the structure is initialized with the
46 * knowledge that all current implementations have 2 TSEC
47 * devices, and one FEC. The information needed is:
48 * phyaddr - The address of the PHY which is attached to
51 * gigabit - This variable indicates whether the device
52 * supports gigabit speed ethernet
54 * phyregidx - This variable specifies which ethernet device
55 * controls the MII Management registers which are connected
56 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
57 * access to the PHYs, so all of the entries have "0".
59 * The values specified in the table are taken from the board's
60 * config file in include/configs/. When implementing a new
61 * board with ethernet capability, it is necessary to define:
71 static struct tsec_info_struct tsec_info[] = {
72 #ifdef CONFIG_MPC85XX_TSEC1
73 {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
77 #ifdef CONFIG_MPC85XX_TSEC2
78 {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
82 #ifdef CONFIG_MPC85XX_FEC
83 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
89 #define MAXCONTROLLERS 3
91 static int relocated = 0;
93 static struct tsec_private *privlist[MAXCONTROLLERS];
96 static RTXBD rtx __attribute__ ((aligned(8)));
98 #error "rtx must be 64-bit aligned"
101 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
102 static int tsec_recv(struct eth_device* dev);
103 static int tsec_init(struct eth_device* dev, bd_t * bd);
104 static void tsec_halt(struct eth_device* dev);
105 static void init_registers(volatile tsec_t *regs);
106 static void startup_tsec(struct eth_device *dev);
107 static int init_phy(struct eth_device *dev);
108 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
109 uint read_phy_reg(struct tsec_private *priv, uint regnum);
110 struct phy_info * get_phy_info(struct eth_device *dev);
111 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
112 static void adjust_link(struct eth_device *dev);
113 static void relocate_cmds(void);
115 /* Initialize device structure. Returns success if PHY
116 * initialization succeeded (i.e. if it recognizes the PHY)
118 int tsec_initialize(bd_t *bis, int index)
120 struct eth_device* dev;
122 struct tsec_private *priv;
124 dev = (struct eth_device*) malloc(sizeof *dev);
129 memset(dev, 0, sizeof *dev);
131 priv = (struct tsec_private *) malloc(sizeof(*priv));
136 privlist[index] = priv;
137 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
138 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
139 tsec_info[index].phyregidx*TSEC_SIZE);
141 priv->phyaddr = tsec_info[index].phyaddr;
142 priv->gigabit = tsec_info[index].gigabit;
144 sprintf(dev->name, "MOTO ENET%d", index);
147 dev->init = tsec_init;
148 dev->halt = tsec_halt;
149 dev->send = tsec_send;
150 dev->recv = tsec_recv;
152 /* Tell u-boot to get the addr from the env */
154 dev->enetaddr[i] = 0;
160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
161 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
163 /* Try to initialize PHY here, and return */
164 return init_phy(dev);
168 /* Initializes data structures and registers for the controller,
169 * and brings the interface up. Returns the link status, meaning
170 * that it returns success if the link is up, failure otherwise.
171 * This allows u-boot to find the first active controller. */
172 int tsec_init(struct eth_device* dev, bd_t * bd)
175 char tmpbuf[MAC_ADDR_LEN];
177 struct tsec_private *priv = (struct tsec_private *)dev->priv;
178 volatile tsec_t *regs = priv->regs;
180 /* Make sure the controller is stopped */
183 /* Init MACCFG2. Defaults to GMII */
184 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
187 regs->ecntrl = ECNTRL_INIT_SETTINGS;
189 /* Copy the station address into the address registers.
190 * Backwards, because little endian MACS are dumb */
191 for(i=0;i<MAC_ADDR_LEN;i++) {
192 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
194 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
196 tempval = *((uint *)(tmpbuf +4));
198 (uint)(regs->macstnaddr2) = tempval;
200 /* reset the indices to zero */
204 /* Clear out (for the most part) the other registers */
205 init_registers(regs);
207 /* Ready the device for tx/rx */
210 /* If there's no link, fail */
216 /* Write value to the device's PHY through the registers
217 * specified in priv, modifying the register specified in regnum.
218 * It will wait for the write to be done (or for a timeout to
219 * expire) before exiting
221 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
223 volatile tsec_t *regbase = priv->phyregs;
224 uint phyid = priv->phyaddr;
227 regbase->miimadd = (phyid << 8) | regnum;
228 regbase->miimcon = value;
232 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
236 /* Reads register regnum on the device's PHY through the
237 * registers specified in priv. It lowers and raises the read
238 * command, and waits for the data to become valid (miimind
239 * notvalid bit cleared), and the bus to cease activity (miimind
240 * busy bit cleared), and then returns the value
242 uint read_phy_reg(struct tsec_private *priv, uint regnum)
245 volatile tsec_t *regbase = priv->phyregs;
246 uint phyid = priv->phyaddr;
248 /* Put the address of the phy, and the register
249 * number into MIIMADD */
250 regbase->miimadd = (phyid << 8) | regnum;
252 /* Clear the command register, and wait */
253 regbase->miimcom = 0;
256 /* Initiate a read command, and wait */
257 regbase->miimcom = MIIM_READ_COMMAND;
260 /* Wait for the the indication that the read is done */
261 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
263 /* Grab the value read from the PHY */
264 value = regbase->miimstat;
270 /* Discover which PHY is attached to the device, and configure it
271 * properly. If the PHY is not recognized, then return 0
272 * (failure). Otherwise, return 1
274 static int init_phy(struct eth_device *dev)
276 struct tsec_private *priv = (struct tsec_private *)dev->priv;
277 struct phy_info *curphy;
279 /* Assign a Physical address to the TBI */
280 priv->regs->tbipa=TBIPA_VALUE;
285 /* Get the cmd structure corresponding to the attached
287 curphy = get_phy_info(dev);
290 printf("%s: No PHY found\n", dev->name);
295 priv->phyinfo = curphy;
297 phy_run_commands(priv, priv->phyinfo->config);
303 /* Returns which value to write to the control register. */
304 /* For 10/100, the value is slightly different */
305 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
308 return MIIM_CONTROL_INIT;
314 /* Parse the status register for link, and then do
315 * auto-negotiation */
316 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
318 uint timeout = TSEC_TIMEOUT;
320 if(mii_reg & MIIM_STATUS_LINK)
326 while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
327 mii_reg = read_phy_reg(priv, MIIM_STATUS);
334 /* Parse the 88E1011's status register for speed and duplex
336 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
340 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
345 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
348 case MIIM_88E1011_PHYSTAT_GBIT:
351 case MIIM_88E1011_PHYSTAT_100:
362 /* Parse the cis8201's status register for speed and duplex
364 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
368 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
373 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
375 case MIIM_CIS8201_AUXCONSTAT_GBIT:
378 case MIIM_CIS8201_AUXCONSTAT_100:
390 /* Parse the DM9161's status register for speed and duplex
392 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
394 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
399 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
408 /* Hack to write all 4 PHYs with the LED values */
409 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
412 volatile tsec_t *regbase = priv->phyregs;
415 for(phyid=0;phyid<4;phyid++) {
416 regbase->miimadd = (phyid << 8) | mii_reg;
417 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
421 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
424 return MIIM_CIS8204_SLEDCON_INIT;
428 /* Initialized required registers to appropriate values, zeroing
429 * those we don't care about (unless zero is bad, in which case,
430 * choose a more appropriate value) */
431 static void init_registers(volatile tsec_t *regs)
434 regs->ievent = IEVENT_INIT_CLEAR;
436 regs->imask = IMASK_INIT_CLEAR;
438 regs->hash.iaddr0 = 0;
439 regs->hash.iaddr1 = 0;
440 regs->hash.iaddr2 = 0;
441 regs->hash.iaddr3 = 0;
442 regs->hash.iaddr4 = 0;
443 regs->hash.iaddr5 = 0;
444 regs->hash.iaddr6 = 0;
445 regs->hash.iaddr7 = 0;
447 regs->hash.gaddr0 = 0;
448 regs->hash.gaddr1 = 0;
449 regs->hash.gaddr2 = 0;
450 regs->hash.gaddr3 = 0;
451 regs->hash.gaddr4 = 0;
452 regs->hash.gaddr5 = 0;
453 regs->hash.gaddr6 = 0;
454 regs->hash.gaddr7 = 0;
456 regs->rctrl = 0x00000000;
458 /* Init RMON mib registers */
459 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
461 regs->rmon.cam1 = 0xffffffff;
462 regs->rmon.cam2 = 0xffffffff;
464 regs->mrblr = MRBLR_INIT_SETTINGS;
466 regs->minflr = MINFLR_INIT_SETTINGS;
468 regs->attr = ATTR_INIT_SETTINGS;
469 regs->attreli = ATTRELI_INIT_SETTINGS;
474 /* Configure maccfg2 based on negotiated speed and duplex
475 * reported by PHY handling code */
476 static void adjust_link(struct eth_device *dev)
478 struct tsec_private *priv = (struct tsec_private *)dev->priv;
479 volatile tsec_t *regs = priv->regs;
482 if(priv->duplexity != 0)
483 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
485 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
487 switch(priv->speed) {
489 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
494 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
498 printf("%s: Speed was bad\n", dev->name);
502 printf("Speed: %d, %s duplex\n", priv->speed,
503 (priv->duplexity) ? "full" : "half");
506 printf("%s: No link.\n", dev->name);
511 /* Set up the buffers and their descriptors, and bring up the
513 static void startup_tsec(struct eth_device *dev)
516 struct tsec_private *priv = (struct tsec_private *)dev->priv;
517 volatile tsec_t *regs = priv->regs;
519 /* Point to the buffer descriptors */
520 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
521 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
523 /* Initialize the Rx Buffer descriptors */
524 for (i = 0; i < PKTBUFSRX; i++) {
525 rtx.rxbd[i].status = RXBD_EMPTY;
526 rtx.rxbd[i].length = 0;
527 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
529 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
531 /* Initialize the TX Buffer Descriptors */
532 for(i=0; i<TX_BUF_CNT; i++) {
533 rtx.txbd[i].status = 0;
534 rtx.txbd[i].length = 0;
535 rtx.txbd[i].bufPtr = 0;
537 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
539 /* Start up the PHY */
540 phy_run_commands(priv, priv->phyinfo->startup);
543 /* Enable Transmit and Receive */
544 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
546 /* Tell the DMA it is clear to go */
547 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
548 regs->tstat = TSTAT_CLEAR_THALT;
549 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
552 /* This returns the status bits of the device. The return value
553 * is never checked, and this is what the 8260 driver did, so we
554 * do the same. Presumably, this would be zero if there were no
556 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
560 struct tsec_private *priv = (struct tsec_private *)dev->priv;
561 volatile tsec_t *regs = priv->regs;
563 /* Find an empty buffer descriptor */
564 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
565 if (i >= TOUT_LOOP) {
566 debug ("%s: tsec: tx buffers full\n", dev->name);
571 rtx.txbd[txIdx].bufPtr = (uint)packet;
572 rtx.txbd[txIdx].length = length;
573 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
575 /* Tell the DMA to go */
576 regs->tstat = TSTAT_CLEAR_THALT;
578 /* Wait for buffer to be transmitted */
579 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
580 if (i >= TOUT_LOOP) {
581 debug ("%s: tsec: tx error\n", dev->name);
586 txIdx = (txIdx + 1) % TX_BUF_CNT;
587 result = rtx.txbd[txIdx].status & TXBD_STATS;
592 static int tsec_recv(struct eth_device* dev)
595 struct tsec_private *priv = (struct tsec_private *)dev->priv;
596 volatile tsec_t *regs = priv->regs;
598 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
600 length = rtx.rxbd[rxIdx].length;
602 /* Send the packet up if there were no errors */
603 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
604 NetReceive(NetRxPackets[rxIdx], length - 4);
606 printf("Got error %x\n",
607 (rtx.rxbd[rxIdx].status & RXBD_STATS));
610 rtx.rxbd[rxIdx].length = 0;
612 /* Set the wrap bit if this is the last element in the list */
613 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
615 rxIdx = (rxIdx + 1) % PKTBUFSRX;
618 if(regs->ievent&IEVENT_BSY) {
619 regs->ievent = IEVENT_BSY;
620 regs->rstat = RSTAT_CLEAR_RHALT;
628 /* Stop the interface */
629 static void tsec_halt(struct eth_device* dev)
631 struct tsec_private *priv = (struct tsec_private *)dev->priv;
632 volatile tsec_t *regs = priv->regs;
634 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
635 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
637 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
639 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
641 /* Shut down the PHY, as needed */
642 phy_run_commands(priv, priv->phyinfo->shutdown);
646 struct phy_info phy_info_M88E1011S = {
650 (struct phy_cmd[]) { /* config */
651 /* Reset and configure the PHY */
652 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
654 {0x1e, 0x200c, NULL},
658 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
659 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
660 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
661 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
664 (struct phy_cmd[]) { /* startup */
665 /* Status is read once to clear old link state */
666 {MIIM_STATUS, miim_read, NULL},
668 {MIIM_STATUS, miim_read, &mii_parse_sr},
669 /* Read the status */
670 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
673 (struct phy_cmd[]) { /* shutdown */
678 struct phy_info phy_info_M88E1111S = {
682 (struct phy_cmd[]) { /* config */
683 /* Reset and configure the PHY */
684 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
686 {0x1e, 0x200c, NULL},
690 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
691 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
692 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
693 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
696 (struct phy_cmd[]) { /* startup */
697 /* Status is read once to clear old link state */
698 {MIIM_STATUS, miim_read, NULL},
700 {MIIM_STATUS, miim_read, &mii_parse_sr},
701 /* Read the status */
702 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
705 (struct phy_cmd[]) { /* shutdown */
710 struct phy_info phy_info_cis8204 = {
714 (struct phy_cmd[]) { /* config */
715 /* Override PHY config settings */
716 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
717 /* Configure some basic stuff */
718 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
719 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
720 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
723 (struct phy_cmd[]) { /* startup */
724 /* Read the Status (2x to make sure link is right) */
725 {MIIM_STATUS, miim_read, NULL},
727 {MIIM_STATUS, miim_read, &mii_parse_sr},
728 /* Read the status */
729 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
732 (struct phy_cmd[]) { /* shutdown */
738 struct phy_info phy_info_cis8201 = {
742 (struct phy_cmd[]) { /* config */
743 /* Override PHY config settings */
744 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
745 /* Set up the interface mode */
746 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
747 /* Configure some basic stuff */
748 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
751 (struct phy_cmd[]) { /* startup */
752 /* Read the Status (2x to make sure link is right) */
753 {MIIM_STATUS, miim_read, NULL},
755 {MIIM_STATUS, miim_read, &mii_parse_sr},
756 /* Read the status */
757 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
760 (struct phy_cmd[]) { /* shutdown */
766 struct phy_info phy_info_dm9161 = {
770 (struct phy_cmd[]) { /* config */
771 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
772 /* Do not bypass the scrambler/descrambler */
773 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
774 /* Clear 10BTCSR to default */
775 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
776 /* Configure some basic stuff */
777 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
778 /* Restart Auto Negotiation */
779 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
782 (struct phy_cmd[]) { /* startup */
783 /* Status is read once to clear old link state */
784 {MIIM_STATUS, miim_read, NULL},
786 {MIIM_STATUS, miim_read, &mii_parse_sr},
787 /* Read the status */
788 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
791 (struct phy_cmd[]) { /* shutdown */
796 static struct phy_info phy_info_lxt971 = {
800 (struct phy_cmd []) { /* config */
801 { MIIM_CONTROL, MIIM_CONTROL_INIT, mii_cr_init }, /* autonegotiate */
804 (struct phy_cmd []) { /* startup - enable interrupts */
805 /* { 0x12, 0x00f2, NULL }, */
806 { 0x14, 0xd422, NULL }, /* LED config */
807 { MIIM_STATUS, miim_read, NULL },
808 { MIIM_STATUS, miim_read, mii_parse_sr },
811 (struct phy_cmd []) { /* shutdown - disable interrupts */
816 struct phy_info *phy_info[] = {
829 /* Grab the identifier of the device's PHY, and search through
830 * all of the known PHYs to see if one matches. If so, return
831 * it, if not, return NULL */
832 struct phy_info * get_phy_info(struct eth_device *dev)
834 struct tsec_private *priv = (struct tsec_private *)dev->priv;
835 uint phy_reg, phy_ID;
837 struct phy_info *theInfo = NULL;
839 /* Grab the bits from PHYIR1, and put them in the upper half */
840 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
841 phy_ID = (phy_reg & 0xffff) << 16;
843 /* Grab the bits from PHYIR2, and put them in the lower half */
844 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
845 phy_ID |= (phy_reg & 0xffff);
847 /* loop through all the known PHY types, and find one that */
848 /* matches the ID we read from the PHY. */
849 for(i=0; phy_info[i]; i++) {
850 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
851 theInfo = phy_info[i];
856 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
859 printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
867 /* Execute the given series of commands on the given device's
868 * PHY, running functions as necessary*/
869 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
873 volatile tsec_t *phyregs = priv->phyregs;
875 phyregs->miimcfg = MIIMCFG_RESET;
877 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
879 while(phyregs->miimind & MIIMIND_BUSY);
881 for(i=0;cmd->mii_reg != miim_end;i++) {
882 if(cmd->mii_data == miim_read) {
883 result = read_phy_reg(priv, cmd->mii_reg);
885 if(cmd->funct != NULL)
886 (*(cmd->funct))(result, priv);
889 if(cmd->funct != NULL)
890 result = (*(cmd->funct))(cmd->mii_reg, priv);
892 result = cmd->mii_data;
894 write_phy_reg(priv, cmd->mii_reg, result);
902 /* Relocate the function pointers in the phy cmd lists */
903 static void relocate_cmds(void)
905 struct phy_cmd **cmdlistptr;
908 DECLARE_GLOBAL_DATA_PTR;
910 for(i=0; phy_info[i]; i++) {
911 /* First thing's first: relocate the pointers to the
912 * PHY command structures (the structs were done) */
913 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
915 phy_info[i]->name += gd->reloc_off;
916 phy_info[i]->config =
917 (struct phy_cmd *)((uint)phy_info[i]->config
919 phy_info[i]->startup =
920 (struct phy_cmd *)((uint)phy_info[i]->startup
922 phy_info[i]->shutdown =
923 (struct phy_cmd *)((uint)phy_info[i]->shutdown
926 cmdlistptr = &phy_info[i]->config;
928 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
930 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
931 /* Only relocate non-NULL pointers */
933 cmd->funct += gd->reloc_off;
945 #ifndef CONFIG_BITBANGMII
947 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
951 for(i=0;i<MAXCONTROLLERS;i++) {
952 if(privlist[i]->phyaddr == phyaddr)
960 * Read a MII PHY register.
965 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
968 struct tsec_private *priv = get_priv_for_phy(addr);
971 printf("Can't read PHY at address %d\n", addr);
975 ret = (unsigned short)read_phy_reg(priv, reg);
982 * Write a MII PHY register.
987 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
989 struct tsec_private *priv = get_priv_for_phy(addr);
992 printf("Can't write PHY at address %d\n", addr);
996 write_phy_reg(priv, reg, value);
1001 #endif /* CONFIG_BITBANGMII */
1003 #endif /* CONFIG_TSEC_ENET */