3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
11 * maintained by Jon Loeliger (loeliger@freescale.com)
23 #if defined(CONFIG_TSEC_ENET)
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 struct tsec_info_struct {
39 unsigned int phyregidx;
43 /* The tsec_info structure contains 3 values which the
44 * driver uses to determine how to operate a given ethernet
45 * device. For now, the structure is initialized with the
46 * knowledge that all current implementations have 2 TSEC
47 * devices, and one FEC. The information needed is:
48 * phyaddr - The address of the PHY which is attached to
51 * gigabit - This variable indicates whether the device
52 * supports gigabit speed ethernet
54 * phyregidx - This variable specifies which ethernet device
55 * controls the MII Management registers which are connected
56 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
57 * access to the PHYs, so all of the entries have "0".
59 * The values specified in the table are taken from the board's
60 * config file in include/configs/. When implementing a new
61 * board with ethernet capability, it is necessary to define:
71 static struct tsec_info_struct tsec_info[] = {
72 #ifdef CONFIG_MPC85XX_TSEC1
73 {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
77 #ifdef CONFIG_MPC85XX_TSEC2
78 {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
82 #ifdef CONFIG_MPC85XX_FEC
83 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
89 #define MAXCONTROLLERS 3
91 static int relocated = 0;
93 static struct tsec_private *privlist[MAXCONTROLLERS];
96 static RTXBD rtx __attribute__ ((aligned(8)));
98 #error "rtx must be 64-bit aligned"
101 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
102 static int tsec_recv(struct eth_device* dev);
103 static int tsec_init(struct eth_device* dev, bd_t * bd);
104 static void tsec_halt(struct eth_device* dev);
105 static void init_registers(volatile tsec_t *regs);
106 static void startup_tsec(struct eth_device *dev);
107 static int init_phy(struct eth_device *dev);
108 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
109 uint read_phy_reg(struct tsec_private *priv, uint regnum);
110 struct phy_info * get_phy_info(struct eth_device *dev);
111 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
112 static void adjust_link(struct eth_device *dev);
113 static void relocate_cmds(void);
115 /* Initialize device structure. Returns success if PHY
116 * initialization succeeded (i.e. if it recognizes the PHY)
118 int tsec_initialize(bd_t *bis, int index)
120 struct eth_device* dev;
122 struct tsec_private *priv;
124 dev = (struct eth_device*) malloc(sizeof *dev);
129 memset(dev, 0, sizeof *dev);
131 priv = (struct tsec_private *) malloc(sizeof(*priv));
136 privlist[index] = priv;
137 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
138 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
139 tsec_info[index].phyregidx*TSEC_SIZE);
141 priv->phyaddr = tsec_info[index].phyaddr;
142 priv->gigabit = tsec_info[index].gigabit;
144 sprintf(dev->name, "ENET%d", index);
147 dev->init = tsec_init;
148 dev->halt = tsec_halt;
149 dev->send = tsec_send;
150 dev->recv = tsec_recv;
152 /* Tell u-boot to get the addr from the env */
154 dev->enetaddr[i] = 0;
160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
161 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
163 /* Try to initialize PHY here, and return */
164 return init_phy(dev);
168 /* Initializes data structures and registers for the controller,
169 * and brings the interface up. Returns the link status, meaning
170 * that it returns success if the link is up, failure otherwise.
171 * This allows u-boot to find the first active controller. */
172 int tsec_init(struct eth_device* dev, bd_t * bd)
175 char tmpbuf[MAC_ADDR_LEN];
177 struct tsec_private *priv = (struct tsec_private *)dev->priv;
178 volatile tsec_t *regs = priv->regs;
180 /* Make sure the controller is stopped */
183 /* Init MACCFG2. Defaults to GMII */
184 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
187 regs->ecntrl = ECNTRL_INIT_SETTINGS;
189 /* Copy the station address into the address registers.
190 * Backwards, because little endian MACS are dumb */
191 for(i=0;i<MAC_ADDR_LEN;i++) {
192 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
194 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
196 tempval = *((uint *)(tmpbuf +4));
198 (uint)(regs->macstnaddr2) = tempval;
200 /* reset the indices to zero */
204 /* Clear out (for the most part) the other registers */
205 init_registers(regs);
207 /* Ready the device for tx/rx */
210 /* If there's no link, fail */
216 /* Write value to the device's PHY through the registers
217 * specified in priv, modifying the register specified in regnum.
218 * It will wait for the write to be done (or for a timeout to
219 * expire) before exiting
221 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
223 volatile tsec_t *regbase = priv->phyregs;
224 uint phyid = priv->phyaddr;
227 regbase->miimadd = (phyid << 8) | regnum;
228 regbase->miimcon = value;
232 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
236 /* Reads register regnum on the device's PHY through the
237 * registers specified in priv. It lowers and raises the read
238 * command, and waits for the data to become valid (miimind
239 * notvalid bit cleared), and the bus to cease activity (miimind
240 * busy bit cleared), and then returns the value
242 uint read_phy_reg(struct tsec_private *priv, uint regnum)
245 volatile tsec_t *regbase = priv->phyregs;
246 uint phyid = priv->phyaddr;
248 /* Put the address of the phy, and the register
249 * number into MIIMADD */
250 regbase->miimadd = (phyid << 8) | regnum;
252 /* Clear the command register, and wait */
253 regbase->miimcom = 0;
256 /* Initiate a read command, and wait */
257 regbase->miimcom = MIIM_READ_COMMAND;
260 /* Wait for the the indication that the read is done */
261 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
263 /* Grab the value read from the PHY */
264 value = regbase->miimstat;
270 /* Discover which PHY is attached to the device, and configure it
271 * properly. If the PHY is not recognized, then return 0
272 * (failure). Otherwise, return 1
274 static int init_phy(struct eth_device *dev)
276 struct tsec_private *priv = (struct tsec_private *)dev->priv;
277 struct phy_info *curphy;
279 /* Assign a Physical address to the TBI */
282 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
283 regs->tbipa = TBIPA_VALUE;
284 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
285 regs->tbipa = TBIPA_VALUE;
289 /* Reset MII (due to new addresses) */
290 priv->phyregs->miimcfg = MIIMCFG_RESET;
292 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
294 while(priv->phyregs->miimind & MIIMIND_BUSY);
299 /* Get the cmd structure corresponding to the attached
301 curphy = get_phy_info(dev);
304 printf("%s: No PHY found\n", dev->name);
309 priv->phyinfo = curphy;
311 phy_run_commands(priv, priv->phyinfo->config);
317 /* Returns which value to write to the control register. */
318 /* For 10/100, the value is slightly different */
319 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
322 return MIIM_CONTROL_INIT;
328 /* Parse the status register for link, and then do
329 * auto-negotiation */
330 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
332 uint timeout = TSEC_TIMEOUT;
334 if(mii_reg & MIIM_STATUS_LINK)
340 while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
341 mii_reg = read_phy_reg(priv, MIIM_STATUS);
348 /* Parse the 88E1011's status register for speed and duplex
350 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
354 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
359 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
362 case MIIM_88E1011_PHYSTAT_GBIT:
365 case MIIM_88E1011_PHYSTAT_100:
376 /* Parse the cis8201's status register for speed and duplex
378 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
382 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
387 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
389 case MIIM_CIS8201_AUXCONSTAT_GBIT:
392 case MIIM_CIS8201_AUXCONSTAT_100:
404 /* Parse the DM9161's status register for speed and duplex
406 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
408 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
413 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
422 /* Hack to write all 4 PHYs with the LED values */
423 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
426 volatile tsec_t *regbase = priv->phyregs;
429 for(phyid=0;phyid<4;phyid++) {
430 regbase->miimadd = (phyid << 8) | mii_reg;
431 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
435 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
438 return MIIM_CIS8204_SLEDCON_INIT;
442 /* Initialized required registers to appropriate values, zeroing
443 * those we don't care about (unless zero is bad, in which case,
444 * choose a more appropriate value) */
445 static void init_registers(volatile tsec_t *regs)
448 regs->ievent = IEVENT_INIT_CLEAR;
450 regs->imask = IMASK_INIT_CLEAR;
452 regs->hash.iaddr0 = 0;
453 regs->hash.iaddr1 = 0;
454 regs->hash.iaddr2 = 0;
455 regs->hash.iaddr3 = 0;
456 regs->hash.iaddr4 = 0;
457 regs->hash.iaddr5 = 0;
458 regs->hash.iaddr6 = 0;
459 regs->hash.iaddr7 = 0;
461 regs->hash.gaddr0 = 0;
462 regs->hash.gaddr1 = 0;
463 regs->hash.gaddr2 = 0;
464 regs->hash.gaddr3 = 0;
465 regs->hash.gaddr4 = 0;
466 regs->hash.gaddr5 = 0;
467 regs->hash.gaddr6 = 0;
468 regs->hash.gaddr7 = 0;
470 regs->rctrl = 0x00000000;
472 /* Init RMON mib registers */
473 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
475 regs->rmon.cam1 = 0xffffffff;
476 regs->rmon.cam2 = 0xffffffff;
478 regs->mrblr = MRBLR_INIT_SETTINGS;
480 regs->minflr = MINFLR_INIT_SETTINGS;
482 regs->attr = ATTR_INIT_SETTINGS;
483 regs->attreli = ATTRELI_INIT_SETTINGS;
488 /* Configure maccfg2 based on negotiated speed and duplex
489 * reported by PHY handling code */
490 static void adjust_link(struct eth_device *dev)
492 struct tsec_private *priv = (struct tsec_private *)dev->priv;
493 volatile tsec_t *regs = priv->regs;
496 if(priv->duplexity != 0)
497 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
499 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
501 switch(priv->speed) {
503 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
508 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
512 printf("%s: Speed was bad\n", dev->name);
516 printf("Speed: %d, %s duplex\n", priv->speed,
517 (priv->duplexity) ? "full" : "half");
520 printf("%s: No link.\n", dev->name);
525 /* Set up the buffers and their descriptors, and bring up the
527 static void startup_tsec(struct eth_device *dev)
530 struct tsec_private *priv = (struct tsec_private *)dev->priv;
531 volatile tsec_t *regs = priv->regs;
533 /* Point to the buffer descriptors */
534 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
535 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
537 /* Initialize the Rx Buffer descriptors */
538 for (i = 0; i < PKTBUFSRX; i++) {
539 rtx.rxbd[i].status = RXBD_EMPTY;
540 rtx.rxbd[i].length = 0;
541 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
543 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
545 /* Initialize the TX Buffer Descriptors */
546 for(i=0; i<TX_BUF_CNT; i++) {
547 rtx.txbd[i].status = 0;
548 rtx.txbd[i].length = 0;
549 rtx.txbd[i].bufPtr = 0;
551 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
553 /* Start up the PHY */
554 phy_run_commands(priv, priv->phyinfo->startup);
557 /* Enable Transmit and Receive */
558 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
560 /* Tell the DMA it is clear to go */
561 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
562 regs->tstat = TSTAT_CLEAR_THALT;
563 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
566 /* This returns the status bits of the device. The return value
567 * is never checked, and this is what the 8260 driver did, so we
568 * do the same. Presumably, this would be zero if there were no
570 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
574 struct tsec_private *priv = (struct tsec_private *)dev->priv;
575 volatile tsec_t *regs = priv->regs;
577 /* Find an empty buffer descriptor */
578 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
579 if (i >= TOUT_LOOP) {
580 debug ("%s: tsec: tx buffers full\n", dev->name);
585 rtx.txbd[txIdx].bufPtr = (uint)packet;
586 rtx.txbd[txIdx].length = length;
587 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
589 /* Tell the DMA to go */
590 regs->tstat = TSTAT_CLEAR_THALT;
592 /* Wait for buffer to be transmitted */
593 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
594 if (i >= TOUT_LOOP) {
595 debug ("%s: tsec: tx error\n", dev->name);
600 txIdx = (txIdx + 1) % TX_BUF_CNT;
601 result = rtx.txbd[txIdx].status & TXBD_STATS;
606 static int tsec_recv(struct eth_device* dev)
609 struct tsec_private *priv = (struct tsec_private *)dev->priv;
610 volatile tsec_t *regs = priv->regs;
612 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
614 length = rtx.rxbd[rxIdx].length;
616 /* Send the packet up if there were no errors */
617 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
618 NetReceive(NetRxPackets[rxIdx], length - 4);
620 printf("Got error %x\n",
621 (rtx.rxbd[rxIdx].status & RXBD_STATS));
624 rtx.rxbd[rxIdx].length = 0;
626 /* Set the wrap bit if this is the last element in the list */
627 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
629 rxIdx = (rxIdx + 1) % PKTBUFSRX;
632 if(regs->ievent&IEVENT_BSY) {
633 regs->ievent = IEVENT_BSY;
634 regs->rstat = RSTAT_CLEAR_RHALT;
642 /* Stop the interface */
643 static void tsec_halt(struct eth_device* dev)
645 struct tsec_private *priv = (struct tsec_private *)dev->priv;
646 volatile tsec_t *regs = priv->regs;
648 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
649 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
651 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
653 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
655 /* Shut down the PHY, as needed */
656 phy_run_commands(priv, priv->phyinfo->shutdown);
660 struct phy_info phy_info_M88E1011S = {
664 (struct phy_cmd[]) { /* config */
665 /* Reset and configure the PHY */
666 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
668 {0x1e, 0x200c, NULL},
672 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
673 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
674 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
675 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
678 (struct phy_cmd[]) { /* startup */
679 /* Status is read once to clear old link state */
680 {MIIM_STATUS, miim_read, NULL},
682 {MIIM_STATUS, miim_read, &mii_parse_sr},
683 /* Read the status */
684 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
687 (struct phy_cmd[]) { /* shutdown */
692 struct phy_info phy_info_M88E1111S = {
696 (struct phy_cmd[]) { /* config */
697 /* Reset and configure the PHY */
698 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
700 {0x1e, 0x200c, NULL},
704 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
705 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
706 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
707 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
710 (struct phy_cmd[]) { /* startup */
711 /* Status is read once to clear old link state */
712 {MIIM_STATUS, miim_read, NULL},
714 {MIIM_STATUS, miim_read, &mii_parse_sr},
715 /* Read the status */
716 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
719 (struct phy_cmd[]) { /* shutdown */
724 struct phy_info phy_info_cis8204 = {
728 (struct phy_cmd[]) { /* config */
729 /* Override PHY config settings */
730 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
731 /* Configure some basic stuff */
732 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
733 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
734 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
737 (struct phy_cmd[]) { /* startup */
738 /* Read the Status (2x to make sure link is right) */
739 {MIIM_STATUS, miim_read, NULL},
741 {MIIM_STATUS, miim_read, &mii_parse_sr},
742 /* Read the status */
743 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
746 (struct phy_cmd[]) { /* shutdown */
752 struct phy_info phy_info_cis8201 = {
756 (struct phy_cmd[]) { /* config */
757 /* Override PHY config settings */
758 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
759 /* Set up the interface mode */
760 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
761 /* Configure some basic stuff */
762 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
765 (struct phy_cmd[]) { /* startup */
766 /* Read the Status (2x to make sure link is right) */
767 {MIIM_STATUS, miim_read, NULL},
769 {MIIM_STATUS, miim_read, &mii_parse_sr},
770 /* Read the status */
771 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
774 (struct phy_cmd[]) { /* shutdown */
780 struct phy_info phy_info_dm9161 = {
784 (struct phy_cmd[]) { /* config */
785 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
786 /* Do not bypass the scrambler/descrambler */
787 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
788 /* Clear 10BTCSR to default */
789 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
790 /* Configure some basic stuff */
791 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
792 /* Restart Auto Negotiation */
793 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
796 (struct phy_cmd[]) { /* startup */
797 /* Status is read once to clear old link state */
798 {MIIM_STATUS, miim_read, NULL},
800 {MIIM_STATUS, miim_read, &mii_parse_sr},
801 /* Read the status */
802 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
805 (struct phy_cmd[]) { /* shutdown */
810 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
814 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
817 case MIIM_LXT971_SR2_10HDX:
821 case MIIM_LXT971_SR2_10FDX:
825 case MIIM_LXT971_SR2_100HDX:
841 static struct phy_info phy_info_lxt971 = {
845 (struct phy_cmd []) { /* config */
846 { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
849 (struct phy_cmd []) { /* startup - enable interrupts */
850 /* { 0x12, 0x00f2, NULL }, */
851 { MIIM_STATUS, miim_read, NULL },
852 { MIIM_STATUS, miim_read, &mii_parse_sr },
853 { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
856 (struct phy_cmd []) { /* shutdown - disable interrupts */
861 struct phy_info *phy_info[] = {
874 /* Grab the identifier of the device's PHY, and search through
875 * all of the known PHYs to see if one matches. If so, return
876 * it, if not, return NULL */
877 struct phy_info * get_phy_info(struct eth_device *dev)
879 struct tsec_private *priv = (struct tsec_private *)dev->priv;
880 uint phy_reg, phy_ID;
882 struct phy_info *theInfo = NULL;
884 /* Grab the bits from PHYIR1, and put them in the upper half */
885 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
886 phy_ID = (phy_reg & 0xffff) << 16;
888 /* Grab the bits from PHYIR2, and put them in the lower half */
889 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
890 phy_ID |= (phy_reg & 0xffff);
892 /* loop through all the known PHY types, and find one that */
893 /* matches the ID we read from the PHY. */
894 for(i=0; phy_info[i]; i++) {
895 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
896 theInfo = phy_info[i];
901 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
904 printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
912 /* Execute the given series of commands on the given device's
913 * PHY, running functions as necessary*/
914 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
918 volatile tsec_t *phyregs = priv->phyregs;
920 phyregs->miimcfg = MIIMCFG_RESET;
922 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
924 while(phyregs->miimind & MIIMIND_BUSY);
926 for(i=0;cmd->mii_reg != miim_end;i++) {
927 if(cmd->mii_data == miim_read) {
928 result = read_phy_reg(priv, cmd->mii_reg);
930 if(cmd->funct != NULL)
931 (*(cmd->funct))(result, priv);
934 if(cmd->funct != NULL)
935 result = (*(cmd->funct))(cmd->mii_reg, priv);
937 result = cmd->mii_data;
939 write_phy_reg(priv, cmd->mii_reg, result);
947 /* Relocate the function pointers in the phy cmd lists */
948 static void relocate_cmds(void)
950 struct phy_cmd **cmdlistptr;
953 DECLARE_GLOBAL_DATA_PTR;
955 for(i=0; phy_info[i]; i++) {
956 /* First thing's first: relocate the pointers to the
957 * PHY command structures (the structs were done) */
958 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
960 phy_info[i]->name += gd->reloc_off;
961 phy_info[i]->config =
962 (struct phy_cmd *)((uint)phy_info[i]->config
964 phy_info[i]->startup =
965 (struct phy_cmd *)((uint)phy_info[i]->startup
967 phy_info[i]->shutdown =
968 (struct phy_cmd *)((uint)phy_info[i]->shutdown
971 cmdlistptr = &phy_info[i]->config;
973 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
975 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
976 /* Only relocate non-NULL pointers */
978 cmd->funct += gd->reloc_off;
990 #ifndef CONFIG_BITBANGMII
992 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
996 for(i=0;i<MAXCONTROLLERS;i++) {
997 if(privlist[i]->phyaddr == phyaddr)
1005 * Read a MII PHY register.
1010 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
1013 struct tsec_private *priv = get_priv_for_phy(addr);
1016 printf("Can't read PHY at address %d\n", addr);
1020 ret = (unsigned short)read_phy_reg(priv, reg);
1027 * Write a MII PHY register.
1032 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
1034 struct tsec_private *priv = get_priv_for_phy(addr);
1037 printf("Can't write PHY at address %d\n", addr);
1041 write_phy_reg(priv, reg, value);
1046 #endif /* CONFIG_BITBANGMII */
1048 #endif /* CONFIG_TSEC_ENET */