3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
11 * maintained by Jon Loeliger (loeliger@freescale.com)
23 #if defined(CONFIG_TSEC_ENET)
30 #define DBGPRINT(x,y) printf(x,y)
35 static uint rxIdx; /* index of the current RX buffer */
36 static uint txIdx; /* index of the current TX buffer */
38 typedef volatile struct rtxbd {
39 txbd8_t txbd[TX_BUF_CNT];
40 rxbd8_t rxbd[PKTBUFSRX];
43 struct tsec_info_struct {
46 unsigned int phyregidx;
50 /* The tsec_info structure contains 3 values which the
51 * driver uses to determine how to operate a given ethernet
52 * device. For now, the structure is initialized with the
53 * knowledge that all current implementations have 2 TSEC
54 * devices, and one FEC. The information needed is:
55 * phyaddr - The address of the PHY which is attached to
58 * gigabit - This variable indicates whether the device
59 * supports gigabit speed ethernet
61 * phyregidx - This variable specifies which ethernet device
62 * controls the MII Management registers which are connected
63 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
64 * access to the PHYs, so all of the entries have "0".
66 * The values specified in the table are taken from the board's
67 * config file in include/configs/. When implementing a new
68 * board with ethernet capability, it is necessary to define:
78 static struct tsec_info_struct tsec_info[] = {
79 #ifdef CONFIG_MPC85XX_TSEC1
80 {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
82 #ifdef CONFIG_MPC85XX_TSEC2
83 {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
85 #ifdef CONFIG_MPC85XX_FEC
86 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
90 #define MAXCONTROLLERS 3
92 static int relocated = 0;
94 static struct tsec_private *privlist[MAXCONTROLLERS];
97 static RTXBD rtx __attribute__ ((aligned(8)));
99 #error "rtx must be 64-bit aligned"
102 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
103 static int tsec_recv(struct eth_device* dev);
104 static int tsec_init(struct eth_device* dev, bd_t * bd);
105 static void tsec_halt(struct eth_device* dev);
106 static void init_registers(volatile tsec_t *regs);
107 static void startup_tsec(struct eth_device *dev);
108 static int init_phy(struct eth_device *dev);
109 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
110 uint read_phy_reg(struct tsec_private *priv, uint regnum);
111 struct phy_info * get_phy_info(struct eth_device *dev);
112 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
113 static void adjust_link(struct eth_device *dev);
114 static void relocate_cmds(void);
116 /* Initialize device structure. Returns success if PHY
117 * initialization succeeded (i.e. if it recognizes the PHY)
119 int tsec_initialize(bd_t *bis, int index)
121 struct eth_device* dev;
123 struct tsec_private *priv;
125 dev = (struct eth_device*) malloc(sizeof *dev);
130 memset(dev, 0, sizeof *dev);
132 priv = (struct tsec_private *) malloc(sizeof(*priv));
137 privlist[index] = priv;
138 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
139 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
140 tsec_info[index].phyregidx*TSEC_SIZE);
142 priv->phyaddr = tsec_info[index].phyaddr;
143 priv->gigabit = tsec_info[index].gigabit;
145 sprintf(dev->name, "MOTO ENET%d", index);
148 dev->init = tsec_init;
149 dev->halt = tsec_halt;
150 dev->send = tsec_send;
151 dev->recv = tsec_recv;
153 /* Tell u-boot to get the addr from the env */
155 dev->enetaddr[i] = 0;
161 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
164 /* Try to initialize PHY here, and return */
165 return init_phy(dev);
169 /* Initializes data structures and registers for the controller,
170 * and brings the interface up. Returns the link status, meaning
171 * that it returns success if the link is up, failure otherwise.
172 * This allows u-boot to find the first active controller. */
173 int tsec_init(struct eth_device* dev, bd_t * bd)
176 char tmpbuf[MAC_ADDR_LEN];
178 struct tsec_private *priv = (struct tsec_private *)dev->priv;
179 volatile tsec_t *regs = priv->regs;
181 /* Make sure the controller is stopped */
184 /* Init MACCFG2. Defaults to GMII */
185 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
188 regs->ecntrl = ECNTRL_INIT_SETTINGS;
190 /* Copy the station address into the address registers.
191 * Backwards, because little endian MACS are dumb */
192 for(i=0;i<MAC_ADDR_LEN;i++) {
193 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
195 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
197 tempval = *((uint *)(tmpbuf +4));
199 (uint)(regs->macstnaddr2) = tempval;
201 /* reset the indices to zero */
205 /* Clear out (for the most part) the other registers */
206 init_registers(regs);
208 /* Ready the device for tx/rx */
211 /* If there's no link, fail */
217 /* Write value to the device's PHY through the registers
218 * specified in priv, modifying the register specified in regnum.
219 * It will wait for the write to be done (or for a timeout to
220 * expire) before exiting
222 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
224 volatile tsec_t *regbase = priv->phyregs;
225 uint phyid = priv->phyaddr;
228 regbase->miimadd = (phyid << 8) | regnum;
229 regbase->miimcon = value;
233 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
237 /* Reads register regnum on the device's PHY through the
238 * registers specified in priv. It lowers and raises the read
239 * command, and waits for the data to become valid (miimind
240 * notvalid bit cleared), and the bus to cease activity (miimind
241 * busy bit cleared), and then returns the value
243 uint read_phy_reg(struct tsec_private *priv, uint regnum)
246 volatile tsec_t *regbase = priv->phyregs;
247 uint phyid = priv->phyaddr;
249 /* Put the address of the phy, and the register
250 * number into MIIMADD */
251 regbase->miimadd = (phyid << 8) | regnum;
253 /* Clear the command register, and wait */
254 regbase->miimcom = 0;
257 /* Initiate a read command, and wait */
258 regbase->miimcom = MIIM_READ_COMMAND;
261 /* Wait for the the indication that the read is done */
262 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
264 /* Grab the value read from the PHY */
265 value = regbase->miimstat;
271 /* Discover which PHY is attached to the device, and configure it
272 * properly. If the PHY is not recognized, then return 0
273 * (failure). Otherwise, return 1
275 static int init_phy(struct eth_device *dev)
277 struct tsec_private *priv = (struct tsec_private *)dev->priv;
278 struct phy_info *curphy;
280 /* Assign a Physical address to the TBI */
281 priv->regs->tbipa=TBIPA_VALUE;
286 /* Get the cmd structure corresponding to the attached
288 curphy = get_phy_info(dev);
291 printf("%s: No PHY found\n", dev->name);
296 priv->phyinfo = curphy;
298 phy_run_commands(priv, priv->phyinfo->config);
304 /* Returns which value to write to the control register. */
305 /* For 10/100, the value is slightly different */
306 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
309 return MIIM_CONTROL_INIT;
315 /* Parse the status register for link, and then do
316 * auto-negotiation */
317 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
319 uint timeout = TSEC_TIMEOUT;
321 if(mii_reg & MIIM_STATUS_LINK)
327 while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
328 mii_reg = read_phy_reg(priv, MIIM_STATUS);
335 /* Parse the 88E1011's status register for speed and duplex
337 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
341 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
346 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
349 case MIIM_88E1011_PHYSTAT_GBIT:
352 case MIIM_88E1011_PHYSTAT_100:
363 /* Parse the cis8201's status register for speed and duplex
365 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
369 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
374 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
376 case MIIM_CIS8201_AUXCONSTAT_GBIT:
379 case MIIM_CIS8201_AUXCONSTAT_100:
391 /* Parse the DM9161's status register for speed and duplex
393 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
395 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
400 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
409 /* Hack to write all 4 PHYs with the LED values */
410 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
413 volatile tsec_t *regbase = priv->phyregs;
416 for(phyid=0;phyid<4;phyid++) {
417 regbase->miimadd = (phyid << 8) | mii_reg;
418 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
422 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
425 return MIIM_CIS8204_SLEDCON_INIT;
429 /* Initialized required registers to appropriate values, zeroing
430 * those we don't care about (unless zero is bad, in which case,
431 * choose a more appropriate value) */
432 static void init_registers(volatile tsec_t *regs)
435 regs->ievent = IEVENT_INIT_CLEAR;
437 regs->imask = IMASK_INIT_CLEAR;
439 regs->hash.iaddr0 = 0;
440 regs->hash.iaddr1 = 0;
441 regs->hash.iaddr2 = 0;
442 regs->hash.iaddr3 = 0;
443 regs->hash.iaddr4 = 0;
444 regs->hash.iaddr5 = 0;
445 regs->hash.iaddr6 = 0;
446 regs->hash.iaddr7 = 0;
448 regs->hash.gaddr0 = 0;
449 regs->hash.gaddr1 = 0;
450 regs->hash.gaddr2 = 0;
451 regs->hash.gaddr3 = 0;
452 regs->hash.gaddr4 = 0;
453 regs->hash.gaddr5 = 0;
454 regs->hash.gaddr6 = 0;
455 regs->hash.gaddr7 = 0;
457 regs->rctrl = 0x00000000;
459 /* Init RMON mib registers */
460 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
462 regs->rmon.cam1 = 0xffffffff;
463 regs->rmon.cam2 = 0xffffffff;
465 regs->mrblr = MRBLR_INIT_SETTINGS;
467 regs->minflr = MINFLR_INIT_SETTINGS;
469 regs->attr = ATTR_INIT_SETTINGS;
470 regs->attreli = ATTRELI_INIT_SETTINGS;
475 /* Configure maccfg2 based on negotiated speed and duplex
476 * reported by PHY handling code */
477 static void adjust_link(struct eth_device *dev)
479 struct tsec_private *priv = (struct tsec_private *)dev->priv;
480 volatile tsec_t *regs = priv->regs;
483 if(priv->duplexity != 0)
484 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
486 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
488 switch(priv->speed) {
490 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
495 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
499 printf("%s: Speed was bad\n", dev->name);
503 printf("Speed: %d, %s duplex\n", priv->speed,
504 (priv->duplexity) ? "full" : "half");
507 printf("%s: No link.\n", dev->name);
512 /* Set up the buffers and their descriptors, and bring up the
514 static void startup_tsec(struct eth_device *dev)
517 struct tsec_private *priv = (struct tsec_private *)dev->priv;
518 volatile tsec_t *regs = priv->regs;
520 /* Point to the buffer descriptors */
521 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
522 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
524 /* Initialize the Rx Buffer descriptors */
525 for (i = 0; i < PKTBUFSRX; i++) {
526 rtx.rxbd[i].status = RXBD_EMPTY;
527 rtx.rxbd[i].length = 0;
528 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
530 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
532 /* Initialize the TX Buffer Descriptors */
533 for(i=0; i<TX_BUF_CNT; i++) {
534 rtx.txbd[i].status = 0;
535 rtx.txbd[i].length = 0;
536 rtx.txbd[i].bufPtr = 0;
538 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
540 /* Start up the PHY */
541 phy_run_commands(priv, priv->phyinfo->startup);
544 /* Enable Transmit and Receive */
545 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
547 /* Tell the DMA it is clear to go */
548 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
549 regs->tstat = TSTAT_CLEAR_THALT;
550 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
553 /* This returns the status bits of the device. The return value
554 * is never checked, and this is what the 8260 driver did, so we
555 * do the same. Presumably, this would be zero if there were no
557 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
561 struct tsec_private *priv = (struct tsec_private *)dev->priv;
562 volatile tsec_t *regs = priv->regs;
564 /* Find an empty buffer descriptor */
565 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
566 if (i >= TOUT_LOOP) {
567 DBGPRINT("%s: tsec: tx buffers full\n", dev->name);
572 rtx.txbd[txIdx].bufPtr = (uint)packet;
573 rtx.txbd[txIdx].length = length;
574 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
576 /* Tell the DMA to go */
577 regs->tstat = TSTAT_CLEAR_THALT;
579 /* Wait for buffer to be transmitted */
580 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
581 if (i >= TOUT_LOOP) {
582 DBGPRINT("%s: tsec: tx error\n", dev->name);
587 txIdx = (txIdx + 1) % TX_BUF_CNT;
588 result = rtx.txbd[txIdx].status & TXBD_STATS;
593 static int tsec_recv(struct eth_device* dev)
596 struct tsec_private *priv = (struct tsec_private *)dev->priv;
597 volatile tsec_t *regs = priv->regs;
599 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
601 length = rtx.rxbd[rxIdx].length;
603 /* Send the packet up if there were no errors */
604 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
605 NetReceive(NetRxPackets[rxIdx], length - 4);
607 printf("Got error %x\n",
608 (rtx.rxbd[rxIdx].status & RXBD_STATS));
611 rtx.rxbd[rxIdx].length = 0;
613 /* Set the wrap bit if this is the last element in the list */
614 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
616 rxIdx = (rxIdx + 1) % PKTBUFSRX;
619 if(regs->ievent&IEVENT_BSY) {
620 regs->ievent = IEVENT_BSY;
621 regs->rstat = RSTAT_CLEAR_RHALT;
629 /* Stop the interface */
630 static void tsec_halt(struct eth_device* dev)
632 struct tsec_private *priv = (struct tsec_private *)dev->priv;
633 volatile tsec_t *regs = priv->regs;
635 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
636 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
638 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
640 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
642 /* Shut down the PHY, as needed */
643 phy_run_commands(priv, priv->phyinfo->shutdown);
647 struct phy_info phy_info_M88E1011S = {
651 (struct phy_cmd[]) { /* config */
652 /* Reset and configure the PHY */
653 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
655 {0x1e, 0x200c, NULL},
659 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
660 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
661 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
662 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
665 (struct phy_cmd[]) { /* startup */
666 /* Status is read once to clear old link state */
667 {MIIM_STATUS, miim_read, NULL},
669 {MIIM_STATUS, miim_read, &mii_parse_sr},
670 /* Read the status */
671 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
674 (struct phy_cmd[]) { /* shutdown */
679 struct phy_info phy_info_cis8204 = {
683 (struct phy_cmd[]) { /* config */
684 /* Override PHY config settings */
685 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
686 /* Configure some basic stuff */
687 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
688 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
689 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
692 (struct phy_cmd[]) { /* startup */
693 /* Read the Status (2x to make sure link is right) */
694 {MIIM_STATUS, miim_read, NULL},
696 {MIIM_STATUS, miim_read, &mii_parse_sr},
697 /* Read the status */
698 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
701 (struct phy_cmd[]) { /* shutdown */
707 struct phy_info phy_info_cis8201 = {
711 (struct phy_cmd[]) { /* config */
712 /* Override PHY config settings */
713 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
714 /* Set up the interface mode */
715 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
716 /* Configure some basic stuff */
717 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
720 (struct phy_cmd[]) { /* startup */
721 /* Read the Status (2x to make sure link is right) */
722 {MIIM_STATUS, miim_read, NULL},
724 {MIIM_STATUS, miim_read, &mii_parse_sr},
725 /* Read the status */
726 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
729 (struct phy_cmd[]) { /* shutdown */
735 struct phy_info phy_info_dm9161 = {
739 (struct phy_cmd[]) { /* config */
740 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
741 /* Do not bypass the scrambler/descrambler */
742 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
743 /* Clear 10BTCSR to default */
744 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
745 /* Configure some basic stuff */
746 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
747 /* Restart Auto Negotiation */
748 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
751 (struct phy_cmd[]) { /* startup */
752 /* Status is read once to clear old link state */
753 {MIIM_STATUS, miim_read, NULL},
755 {MIIM_STATUS, miim_read, &mii_parse_sr},
756 /* Read the status */
757 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
760 (struct phy_cmd[]) { /* shutdown */
765 struct phy_info *phy_info[] = {
776 /* Grab the identifier of the device's PHY, and search through
777 * all of the known PHYs to see if one matches. If so, return
778 * it, if not, return NULL */
779 struct phy_info * get_phy_info(struct eth_device *dev)
781 struct tsec_private *priv = (struct tsec_private *)dev->priv;
782 uint phy_reg, phy_ID;
784 struct phy_info *theInfo = NULL;
786 /* Grab the bits from PHYIR1, and put them in the upper half */
787 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
788 phy_ID = (phy_reg & 0xffff) << 16;
790 /* Grab the bits from PHYIR2, and put them in the lower half */
791 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
792 phy_ID |= (phy_reg & 0xffff);
794 /* loop through all the known PHY types, and find one that */
795 /* matches the ID we read from the PHY. */
796 for(i=0; phy_info[i]; i++) {
797 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
798 theInfo = phy_info[i];
803 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
806 printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
814 /* Execute the given series of commands on the given device's
815 * PHY, running functions as necessary*/
816 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
820 volatile tsec_t *phyregs = priv->phyregs;
822 phyregs->miimcfg = MIIMCFG_RESET;
824 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
826 while(phyregs->miimind & MIIMIND_BUSY);
828 for(i=0;cmd->mii_reg != miim_end;i++) {
829 if(cmd->mii_data == miim_read) {
830 result = read_phy_reg(priv, cmd->mii_reg);
832 if(cmd->funct != NULL)
833 (*(cmd->funct))(result, priv);
836 if(cmd->funct != NULL)
837 result = (*(cmd->funct))(cmd->mii_reg, priv);
839 result = cmd->mii_data;
841 write_phy_reg(priv, cmd->mii_reg, result);
849 /* Relocate the function pointers in the phy cmd lists */
850 static void relocate_cmds(void)
852 struct phy_cmd **cmdlistptr;
855 DECLARE_GLOBAL_DATA_PTR;
857 for(i=0; phy_info[i]; i++) {
858 /* First thing's first: relocate the pointers to the
859 * PHY command structures (the structs were done) */
860 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
862 phy_info[i]->name += gd->reloc_off;
863 phy_info[i]->config =
864 (struct phy_cmd *)((uint)phy_info[i]->config
866 phy_info[i]->startup =
867 (struct phy_cmd *)((uint)phy_info[i]->startup
869 phy_info[i]->shutdown =
870 (struct phy_cmd *)((uint)phy_info[i]->shutdown
873 cmdlistptr = &phy_info[i]->config;
875 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
877 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
878 /* Only relocate non-NULL pointers */
880 cmd->funct += gd->reloc_off;
892 #ifndef CONFIG_BITBANGMII
894 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
898 for(i=0;i<MAXCONTROLLERS;i++) {
899 if(privlist[i]->phyaddr == phyaddr)
907 * Read a MII PHY register.
912 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
915 struct tsec_private *priv = get_priv_for_phy(addr);
918 printf("Can't read PHY at address %d\n", addr);
922 ret = (unsigned short)read_phy_reg(priv, reg);
929 * Write a MII PHY register.
934 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
936 struct tsec_private *priv = get_priv_for_phy(addr);
939 printf("Can't write PHY at address %d\n", addr);
943 write_phy_reg(priv, reg, value);
948 #endif /* CONFIG_BITBANGMII */
950 #endif /* CONFIG_TSEC_ENET */