2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
48 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
51 * Set up GOT: Global Offset Table
53 * Use r14 to access the GOT
56 GOT_ENTRY(_GOT2_TABLE_)
57 GOT_ENTRY(_FIXUP_TABLE_)
60 GOT_ENTRY(_start_of_vectors)
61 GOT_ENTRY(_end_of_vectors)
62 GOT_ENTRY(transfer_to_handler)
66 GOT_ENTRY(__bss_start)
70 * e500 Startup -- after reset only the last 4KB of the effective
71 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
72 * section is located at THIS LAST page and basically does three
73 * things: clear some registers, set up exception tables and
74 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
75 * continue the boot procedure.
77 * Once the boot rom is mapped by TLB entries we can proceed
78 * with normal startup.
87 /* clear registers/arrays not reset by hardware */
91 mtspr L1CSR0,r0 /* invalidate d-cache */
92 mtspr L1CSR1,r0 /* invalidate i-cache */
95 mtspr DBSR,r1 /* Clear all valid bits */
98 * Enable L1 Caches early
102 lis r2,L1CSR0_CPE@H /* enable parity */
104 mtspr L1CSR0,r2 /* enable L1 Dcache */
106 mtspr L1CSR1,r2 /* enable L1 Icache */
110 /* Setup interrupt vectors */
115 mtspr IVOR0,r1 /* 0: Critical input */
117 mtspr IVOR1,r1 /* 1: Machine check */
119 mtspr IVOR2,r1 /* 2: Data storage */
121 mtspr IVOR3,r1 /* 3: Instruction storage */
123 mtspr IVOR4,r1 /* 4: External interrupt */
125 mtspr IVOR5,r1 /* 5: Alignment */
127 mtspr IVOR6,r1 /* 6: Program check */
129 mtspr IVOR7,r1 /* 7: floating point unavailable */
131 mtspr IVOR8,r1 /* 8: System call */
132 /* 9: Auxiliary processor unavailable(unsupported) */
134 mtspr IVOR10,r1 /* 10: Decrementer */
136 mtspr IVOR11,r1 /* 11: Interval timer */
138 mtspr IVOR12,r1 /* 12: Watchdog timer */
140 mtspr IVOR13,r1 /* 13: Data TLB error */
142 mtspr IVOR14,r1 /* 14: Instruction TLB error */
144 mtspr IVOR15,r1 /* 15: Debug */
146 /* Clear and set up some registers. */
149 mtspr DEC,r0 /* prevent dec exceptions */
150 mttbl r0 /* prevent fit & wdt exceptions */
152 mtspr TSR,r1 /* clear all timer exception status */
153 mtspr TCR,r0 /* disable all */
154 mtspr ESR,r0 /* clear exception syndrome register */
155 mtspr MCSR,r0 /* machine check syndrome register */
156 mtxer r0 /* clear integer exception register */
158 /* Enable Time Base and Select Time Base Clock */
159 lis r0,HID0_EMCP@h /* Enable machine check */
160 #if defined(CONFIG_ENABLE_36BIT_PHYS)
161 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
163 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
166 #ifndef CONFIG_E500MC
167 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
171 /* Enable Branch Prediction */
172 #if defined(CONFIG_BTB)
173 li r0,0x201 /* BBFI = 1, BPEN = 1 */
177 #if defined(CONFIG_SYS_INIT_DBCR)
180 mtspr DBSR,r1 /* Clear all status bits */
181 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
182 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
186 /* create a temp mapping in AS=1 to the boot window */
187 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
188 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
190 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
191 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
193 /* Align the mapping to 16MB */
194 lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
195 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
197 lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
198 ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
208 /* create a temp mapping in AS=1 to the stack */
209 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
210 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
212 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
213 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
215 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
216 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
218 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
219 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
229 lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
230 ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
232 ori r7,r7,switch_as@l
239 /* L1 DCache is used for initial RAM */
241 /* Allocate Initial RAM in data cache.
243 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
244 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
247 /* cache size * 1024 / (2 * L1 line size) */
248 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
254 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
257 /* Jump out the last 4K page and continue to 'normal' start */
258 #ifdef CONFIG_SYS_RAMBOOT
261 /* Calculate absolute address in FLASH and jump there */
262 /*--------------------------------------------------------------*/
263 lis r3,CONFIG_SYS_MONITOR_BASE@h
264 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
265 addi r3,r3,_start_cont - _start + _START_OFFSET
273 .long 0x27051956 /* U-BOOT Magic Number */
274 .globl version_string
276 .ascii U_BOOT_VERSION
277 .ascii " (", __DATE__, " - ", __TIME__, ")"
278 .ascii CONFIG_IDENT_STRING, "\0"
283 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
284 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
285 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
289 stwu r0,-4(r1) /* Terminate call chain */
291 stwu r1,-8(r1) /* Save back chain and move SP */
292 lis r0,RESET_VECTOR@h /* Address of reset vector */
293 ori r0,r0,RESET_VECTOR@l
294 stwu r1,-8(r1) /* Save back chain and move SP */
295 stw r0,+12(r1) /* Save return addr (underflow vect) */
300 /* switch back to AS = 0 */
301 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
302 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
310 . = EXC_OFF_SYS_RESET
311 .globl _start_of_vectors
314 /* Critical input. */
315 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
318 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
320 /* Data Storage exception. */
321 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
323 /* Instruction Storage exception. */
324 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
326 /* External Interrupt exception. */
327 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
329 /* Alignment exception. */
332 EXCEPTION_PROLOG(SRR0, SRR1)
337 addi r3,r1,STACK_FRAME_OVERHEAD
339 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
340 lwz r6,GOT(transfer_to_handler)
344 .long AlignmentException - _start + _START_OFFSET
345 .long int_return - _start + _START_OFFSET
347 /* Program check exception */
350 EXCEPTION_PROLOG(SRR0, SRR1)
351 addi r3,r1,STACK_FRAME_OVERHEAD
353 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
354 lwz r6,GOT(transfer_to_handler)
358 .long ProgramCheckException - _start + _START_OFFSET
359 .long int_return - _start + _START_OFFSET
361 /* No FPU on MPC85xx. This exception is not supposed to happen.
363 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
367 * r0 - SYSCALL number
371 addis r11,r0,0 /* get functions table addr */
372 ori r11,r11,0 /* Note: this code is patched in trap_init */
373 addis r12,r0,0 /* get number of functions */
379 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
383 li r20,0xd00-4 /* Get stack pointer */
385 subi r12,r12,12 /* Adjust stack pointer */
386 li r0,0xc00+_end_back-SystemCall
387 cmplw 0,r0,r12 /* Check stack overflow */
398 li r12,0xc00+_back-SystemCall
406 mfmsr r11 /* Disable interrupts */
410 SYNC /* Some chip revs need this... */
414 li r12,0xd00-4 /* restore regs */
424 addi r12,r12,12 /* Adjust stack pointer */
432 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
433 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
434 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
436 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
437 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
439 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
441 .globl _end_of_vectors
445 . = . + (0x100 - ( . & 0xff )) /* align for debug */
448 * This code finishes saving the registers to the exception frame
449 * and jumps to the appropriate handler for the exception.
450 * Register r21 is pointer into trap frame, r1 has new stack pointer.
452 .globl transfer_to_handler
464 andi. r24,r23,0x3f00 /* get vector offset */
468 mtspr SPRG2,r22 /* r1 is now kernel sp */
470 lwz r24,0(r23) /* virtual address of handler */
471 lwz r23,4(r23) /* where to go when done */
476 rfi /* jump to handler, enable MMU */
479 mfmsr r28 /* Disable interrupts */
483 SYNC /* Some chip revs need this... */
498 lwz r2,_NIP(r1) /* Restore environment */
509 mfmsr r28 /* Disable interrupts */
513 SYNC /* Some chip revs need this... */
528 lwz r2,_NIP(r1) /* Restore environment */
539 mfmsr r28 /* Disable interrupts */
543 SYNC /* Some chip revs need this... */
558 lwz r2,_NIP(r1) /* Restore environment */
570 .globl invalidate_icache
573 ori r0,r0,L1CSR1_ICFI
578 blr /* entire I cache */
580 .globl invalidate_dcache
583 ori r0,r0,L1CSR0_DCFI
603 .globl icache_disable
616 andi. r3,r3,L1CSR1_ICE
634 .globl dcache_disable
647 andi. r3,r3,L1CSR0_DCE
670 /*------------------------------------------------------------------------------- */
672 /* Description: Input 8 bits */
673 /*------------------------------------------------------------------------------- */
679 /*------------------------------------------------------------------------------- */
681 /* Description: Output 8 bits */
682 /*------------------------------------------------------------------------------- */
689 /*------------------------------------------------------------------------------- */
690 /* Function: out16 */
691 /* Description: Output 16 bits */
692 /*------------------------------------------------------------------------------- */
699 /*------------------------------------------------------------------------------- */
700 /* Function: out16r */
701 /* Description: Byte reverse and output 16 bits */
702 /*------------------------------------------------------------------------------- */
709 /*------------------------------------------------------------------------------- */
710 /* Function: out32 */
711 /* Description: Output 32 bits */
712 /*------------------------------------------------------------------------------- */
719 /*------------------------------------------------------------------------------- */
720 /* Function: out32r */
721 /* Description: Byte reverse and output 32 bits */
722 /*------------------------------------------------------------------------------- */
729 /*------------------------------------------------------------------------------- */
731 /* Description: Input 16 bits */
732 /*------------------------------------------------------------------------------- */
738 /*------------------------------------------------------------------------------- */
739 /* Function: in16r */
740 /* Description: Input 16 bits and byte reverse */
741 /*------------------------------------------------------------------------------- */
747 /*------------------------------------------------------------------------------- */
749 /* Description: Input 32 bits */
750 /*------------------------------------------------------------------------------- */
756 /*------------------------------------------------------------------------------- */
757 /* Function: in32r */
758 /* Description: Input 32 bits and byte reverse */
759 /*------------------------------------------------------------------------------- */
765 /*------------------------------------------------------------------------------*/
768 * void relocate_code (addr_sp, gd, addr_moni)
770 * This "function" does not return, instead it continues in RAM
771 * after relocating the monitor code.
775 * r5 = length in bytes
780 mr r1,r3 /* Set new stack pointer */
781 mr r9,r4 /* Save copy of Init Data pointer */
782 mr r10,r5 /* Save copy of Destination Address */
784 mr r3,r5 /* Destination Address */
785 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
786 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
787 lwz r5,GOT(__init_end)
789 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
794 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
800 /* First our own GOT */
802 /* the the one used by the C code */
812 beq cr1,4f /* In place copy is not necessary */
813 beq 7f /* Protect against 0 count */
832 * Now flush the cache: note that we must start from a cache aligned
833 * address. Otherwise we might miss one cache line.
837 beq 7f /* Always flush prefetch queue in any case */
845 sync /* Wait for all dcbst to complete on bus */
851 7: sync /* Wait for all icbi to complete on bus */
855 * Re-point the IVPR at RAM
860 * We are done. Do not return, instead branch to second part of board
861 * initialization, now running from RAM.
864 addi r0,r10,in_ram - _start + _START_OFFSET
866 blr /* NEVER RETURNS! */
871 * Relocation Function, r14 point to got2+0x8000
873 * Adjust got2 pointers, no need to check for 0, this code
874 * already puts a few entries in the table.
876 li r0,__got2_entries@sectoff@l
877 la r3,GOT(_GOT2_TABLE_)
878 lwz r11,GOT(_GOT2_TABLE_)
888 * Now adjust the fixups and the pointers to the fixups
889 * in case we need to move ourselves again.
891 2: li r0,__fixup_entries@sectoff@l
892 lwz r3,GOT(_FIXUP_TABLE_)
906 * Now clear BSS segment
908 lwz r3,GOT(__bss_start)
922 mr r3,r9 /* Init Data pointer */
923 mr r4,r10 /* Destination Address */
927 * Copy exception vector code to low memory
930 * r7: source address, r8: end address, r9: target address
934 lwz r7,GOT(_start_of_vectors)
935 lwz r8,GOT(_end_of_vectors)
937 li r9,0x100 /* reset vector always at 0x100 */
940 bgelr /* return if r7>=r8 - just in case */
942 mflr r4 /* save link register */
952 * relocate `hdlr' and `int_return' entries
954 li r7,.L_CriticalInput - _start + _START_OFFSET
956 li r7,.L_MachineCheck - _start + _START_OFFSET
958 li r7,.L_DataStorage - _start + _START_OFFSET
960 li r7,.L_InstStorage - _start + _START_OFFSET
962 li r7,.L_ExtInterrupt - _start + _START_OFFSET
964 li r7,.L_Alignment - _start + _START_OFFSET
966 li r7,.L_ProgramCheck - _start + _START_OFFSET
968 li r7,.L_FPUnavailable - _start + _START_OFFSET
970 li r7,.L_Decrementer - _start + _START_OFFSET
972 li r7,.L_IntervalTimer - _start + _START_OFFSET
973 li r8,_end_of_vectors - _start + _START_OFFSET
976 addi r7,r7,0x100 /* next exception vector */
983 mtlr r4 /* restore link register */
987 * Function: relocate entries for one exception vector
990 lwz r0,0(r7) /* hdlr ... */
991 add r0,r0,r3 /* ... += dest_addr */
994 lwz r0,4(r7) /* int_return ... */
995 add r0,r0,r3 /* ... += dest_addr */
1000 .globl unlock_ram_in_cache
1001 unlock_ram_in_cache:
1002 /* invalidate the INIT_RAM section */
1003 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1004 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1007 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1010 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1014 /* Invalidate the TLB entries for the cache */
1015 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1016 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1029 mfspr r3,SPRN_L1CFG0
1031 rlwinm r5,r3,9,3 /* Extract cache block size */
1032 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1033 * are currently defined.
1036 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1037 * log2(number of ways)
1039 slw r5,r4,r5 /* r5 = cache block size */
1041 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1042 mulli r7,r7,13 /* An 8-way cache will require 13
1047 /* save off HID0 and set DCFA */
1049 ori r9,r8,HID0_DCFA@l
1056 1: lwz r3,0(r4) /* Load... */
1064 1: dcbf 0,r4 /* ...and flush. */