2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
44 static unsigned int setup_laws_and_tlbs(unsigned int memsize);
48 * Convert picoseconds into clock cycles (rounding up if needed).
52 picos_to_clk(int picos)
56 clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
57 if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
66 * Calculate the Density of each Physical Rank.
67 * Returned size is in bytes.
69 * Study these table from Byte 31 of JEDEC SPD Spec.
83 * Reorder Table to be linear by stripping the bottom
84 * 2 or 5 bits off and shifting them up to the top.
88 compute_banksize(unsigned int mem_type, unsigned char row_dens)
92 if (mem_type == SPD_MEMTYPE_DDR) {
93 /* Bottom 2 bits up to the top. */
94 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
95 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
97 /* Bottom 5 bits up to the top. */
98 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
99 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
106 * Convert a two-nibble BCD value into a cycle time.
107 * While the spec calls for nano-seconds, picos are returned.
109 * This implements the tables for bytes 9, 23 and 25 for both
110 * DDR I and II. No allowance for distinguishing the invalid
111 * fields absent for DDR I yet present in DDR II is made.
112 * (That is, cycle times of .25, .33, .66 and .75 ns are
113 * allowed for both DDR II and I.)
117 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
120 * Table look up the lower nibble, allow DDR I & II.
122 unsigned int tenths_ps[16] = {
141 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
142 unsigned int tenth_ns = spd_val & 0x0F;
143 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
150 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
151 * Table from SPD Spec, Byte 12, converted to picoseconds and
152 * filled in with "default" normal values.
154 unsigned int determine_refresh_rate(unsigned int spd_refresh)
156 unsigned int refresh_time_ns[8] = {
157 15625000, /* 0 Normal 1.00x */
158 3900000, /* 1 Reduced .25x */
159 7800000, /* 2 Extended .50x */
160 31300000, /* 3 Extended 2.00x */
161 62500000, /* 4 Extended 4.00x */
162 125000000, /* 5 Extended 8.00x */
163 15625000, /* 6 Normal 1.00x filler */
164 15625000, /* 7 Normal 1.00x filler */
167 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
174 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
176 unsigned int n_ranks;
177 unsigned int rank_density;
178 unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
179 unsigned int odt_cfg, mode_odt_enable;
180 unsigned int refresh_clk;
181 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
182 unsigned char clk_adjust;
184 unsigned int dqs_cfg;
185 unsigned char twr_clk, twtr_clk, twr_auto_clk;
186 unsigned int tCKmin_ps, tCKmax_ps;
187 unsigned int max_data_rate, effective_data_rate;
188 unsigned int busfreq;
190 unsigned int memsize = 0;
191 unsigned char caslat, caslat_ctrl;
192 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
193 unsigned int trcd_clk;
194 unsigned int trtp_clk;
195 unsigned char cke_min_clk;
196 unsigned char add_lat;
197 unsigned char wr_lat;
198 unsigned char wr_data_delay;
199 unsigned char four_act;
201 unsigned char burst_len;
202 unsigned int mode_caslat;
203 unsigned char sdram_type;
204 unsigned char d_init;
208 * Skip configuration if already configured.
209 * memsize is determined from last configured chip select.
211 if (ddr->cs0_config & 0x80000000) {
212 debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
213 bnds = 0xfff & ddr->cs0_bnds;
214 if (bnds < 0xff) { /* do not add if at top of 4G */
215 memsize = (bnds + 1) << 4;
218 if (ddr->cs1_config & 0x80000000) {
219 debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
220 bnds = 0xfff & ddr->cs1_bnds;
221 if (bnds < 0xff) { /* do not add if at top of 4G */
222 memsize = (bnds + 1) << 4; /* assume ordered bnds */
225 if (ddr->cs2_config & 0x80000000) {
226 debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
227 bnds = 0xfff & ddr->cs2_bnds;
228 if (bnds < 0xff) { /* do not add if at top of 4G */
229 memsize = (bnds + 1) << 4;
232 if (ddr->cs3_config & 0x80000000) {
233 debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
234 bnds = 0xfff & ddr->cs3_bnds;
235 if (bnds < 0xff) { /* do not add if at top of 4G */
236 memsize = (bnds + 1) << 4;
241 printf(" Reusing current %dMB configuration\n",memsize);
242 memsize = setup_laws_and_tlbs(memsize);
243 return memsize << 20;
247 * Read SPD information.
249 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
252 * Check for supported memory module types.
254 if (spd.mem_type != SPD_MEMTYPE_DDR &&
255 spd.mem_type != SPD_MEMTYPE_DDR2) {
256 printf("Unable to locate DDR I or DDR II module.\n"
257 " Fundamental memory type is 0x%0x\n",
263 * These test gloss over DDR I and II differences in interpretation
264 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
265 * are not supported on DDR I; and not encoded on DDR II.
267 * Also note that the 8548 controller can support:
270 * 8 <= ncol <= 11 (still, for DDR)
271 * 6 <= ncol <= 9 (for FCRAM)
273 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
274 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
278 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
279 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
285 * Determine the number of physical banks controlled by
286 * different Chip Select signals. This is not quite the
287 * same as the number of DIMM modules on the board. Feh.
289 if (spd.mem_type == SPD_MEMTYPE_DDR) {
292 n_ranks = (spd.nrows & 0x7) + 1;
295 debug("DDR: number of ranks = %d\n", n_ranks);
298 printf("DDR: Only 2 chip selects are supported: %d\n",
303 #ifdef CONFIG_MPC8548
305 * Adjust DDR II IO voltage biasing.
306 * Only 8548 rev 1 needs the fix
308 if ((SVR_VER(get_svr()) == SVR_8548_E) &&
309 (SVR_MJREV(get_svr()) == 1) &&
310 (spd.mem_type == SPD_MEMTYPE_DDR2)) {
311 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
312 gur->ddrioovcr = (0x80000000 /* Enable */
313 | 0x10000000);/* VSEL to 1.8V */
318 * Determine the size of each Rank in bytes.
320 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
324 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
326 ddr->cs0_bnds = (rank_density >> 24) - 1;
329 * ODT configuration recommendation from DDR Controller Chapter.
331 odt_rd_cfg = 0; /* Never assert ODT */
332 odt_wr_cfg = 0; /* Never assert ODT */
333 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
334 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
336 /* FIXME: How to determine the number of dimm modules? */
337 if (n_dimm_modules == 2) {
338 odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
344 if (spd.nbanks == 0x8)
347 ddr->cs0_config = ( 1 << 31
351 | (spd.nrow_addr - 12) << 8
352 | (spd.ncol_addr - 8) );
354 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
355 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
359 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
361 ddr->cs1_bnds = ( (rank_density >> 8)
362 | ((rank_density >> (24 - 1)) - 1) );
363 ddr->cs1_config = ( 1<<31
366 | (spd.nrow_addr - 12) << 8
367 | (spd.ncol_addr - 8) );
368 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
369 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
374 * Find the largest CAS by locating the highest 1 bit
375 * in the spd.cas_lat field. Translate it to a DDR
376 * controller field value:
378 * CAS Lat DDR I DDR II Ctrl
379 * Clocks SPD Bit SPD Bit Value
380 * ------- ------- ------- -----
391 caslat = __ilog2(spd.cas_lat);
392 if ((spd.mem_type == SPD_MEMTYPE_DDR)
394 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
397 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
398 && (caslat < 2 || caslat > 5)) {
399 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
403 debug("DDR: caslat SPD bit is %d\n", caslat);
406 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
407 * The SPD clk_cycle field (tCKmin) is measured in tenths of
408 * nanoseconds and represented as BCD.
410 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
411 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
414 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
416 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
417 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
421 * Adjust the CAS Latency to allow for bus speeds that
422 * are slower than the DDR module.
424 busfreq = get_ddr_freq(0) / 1000000; /* MHz */
426 effective_data_rate = max_data_rate;
428 /* DDR rate out-of-range */
429 puts("DDR: platform frequency is not fit for DDR rate\n");
432 } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
434 * busfreq 90~230 range, treated as DDR 200.
436 effective_data_rate = 200;
437 if (spd.clk_cycle3 == 0xa0) /* 10 ns */
439 else if (spd.clk_cycle2 == 0xa0)
442 } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
444 * busfreq 230~280 range, treated as DDR 266.
446 effective_data_rate = 266;
447 if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
449 else if (spd.clk_cycle2 == 0x75)
452 } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
454 * busfreq 280~350 range, treated as DDR 333.
456 effective_data_rate = 333;
457 if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
459 else if (spd.clk_cycle2 == 0x60)
462 } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
464 * busfreq 350~460 range, treated as DDR 400.
466 effective_data_rate = 400;
467 if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
469 else if (spd.clk_cycle2 == 0x50)
472 } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
474 * busfreq 460~560 range, treated as DDR 533.
476 effective_data_rate = 533;
477 if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
479 else if (spd.clk_cycle2 == 0x3D)
482 } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
484 * busfreq 560~700 range, treated as DDR 667.
486 effective_data_rate = 667;
487 if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
489 else if (spd.clk_cycle2 == 0x30)
492 } else if (700 <= busfreq) {
494 * DDR rate out-of-range
496 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
497 busfreq, max_data_rate);
503 * Convert caslat clocks to DDR controller value.
504 * Force caslat_ctrl to be DDR Controller field-sized.
506 if (spd.mem_type == SPD_MEMTYPE_DDR) {
507 caslat_ctrl = (caslat + 1) & 0x07;
509 caslat_ctrl = (2 * caslat - 1) & 0x0f;
512 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
513 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
514 caslat, caslat_ctrl);
518 * Avoid writing for DDR I. The new PQ38 DDR controller
519 * dreams up non-zero default values to be backwards compatible.
521 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
522 unsigned char taxpd_clk = 8; /* By the book. */
523 unsigned char tmrd_clk = 2; /* By the book. */
524 unsigned char act_pd_exit = 2; /* Empirical? */
525 unsigned char pre_pd_exit = 6; /* Empirical? */
527 ddr->timing_cfg_0 = (0
528 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
529 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
530 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
531 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
534 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
536 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
541 * Force extra cycles with 0xaa bits.
542 * Incidentally supply the dreamt-up backwards compat value!
544 ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
545 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
546 debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
552 * Some Timing Config 1 values now.
553 * Sneak Extended Refresh Recovery in here too.
557 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
558 * use conservative value.
559 * For DDR II, they are bytes 36 and 37, in quarter nanos.
562 if (spd.mem_type == SPD_MEMTYPE_DDR) {
563 twr_clk = 3; /* Clocks */
564 twtr_clk = 1; /* Clocks */
566 twr_clk = picos_to_clk(spd.twr * 250);
567 twtr_clk = picos_to_clk(spd.twtr * 250);
571 * Calculate Trfc, in picos.
572 * DDR I: Byte 42 straight up in ns.
573 * DDR II: Byte 40 and 42 swizzled some, in ns.
575 if (spd.mem_type == SPD_MEMTYPE_DDR) {
576 trfc = spd.trfc * 1000; /* up to ps */
578 unsigned int byte40_table_ps[8] = {
589 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
590 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
592 trfc_clk = picos_to_clk(trfc);
595 * Trcd, Byte 29, from quarter nanos to ps and clocks.
597 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
600 * Convert trfc_clk to DDR controller fields. DDR I should
601 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
602 * 8548 controller has an extended REFREC field of three bits.
603 * The controller automatically adds 8 clocks to this value,
604 * so preadjust it down 8 first before splitting it up.
606 trfc_low = (trfc_clk - 8) & 0xf;
607 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
610 * Sneak in some Extended Refresh Recovery.
612 ddr->ext_refrec = (trfc_high << 16);
613 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
617 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
618 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
619 | (trcd_clk << 20) /* ACTTORW */
620 | (caslat_ctrl << 16) /* CASLAT */
621 | (trfc_low << 12) /* REFEC */
622 | ((twr_clk & 0x07) << 8) /* WRRREC */
623 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
624 | ((twtr_clk & 0x07) << 0) /* WRTORD */
627 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
638 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
639 * which comes from Trcd, and also note that:
640 * add_lat + caslat must be >= 4
643 if (spd.mem_type == SPD_MEMTYPE_DDR2
644 && (odt_wr_cfg || odt_rd_cfg)
646 add_lat = 4 - caslat;
647 if (add_lat > trcd_clk) {
648 add_lat = trcd_clk - 1;
654 * Historically 0x2 == 4/8 clock delay.
655 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
662 * Minimum CKE Pulse Width.
663 * Four Activate Window
665 if (spd.mem_type == SPD_MEMTYPE_DDR) {
667 * This is a lie. It should really be 1, but if it is
668 * set to 1, bits overlap into the old controller's
669 * otherwise unused ACSM field. If we leave it 0, then
670 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
674 trtp_clk = 2; /* By the book. */
675 cke_min_clk = 1; /* By the book. */
676 four_act = 1; /* By the book. */
681 /* Convert SPD value from quarter nanos to picos. */
682 trtp_clk = picos_to_clk(spd.trtp * 250);
684 cke_min_clk = 3; /* By the book. */
685 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
689 * Empirically set ~MCAS-to-preamble override for DDR 2.
690 * Your milage will vary.
693 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
694 if (effective_data_rate <= 333) {
695 cpo = 0x7; /* READ_LAT + 5/4 */
697 cpo = 0x9; /* READ_LAT + 7/4 */
701 ddr->timing_cfg_2 = (0
702 | ((add_lat & 0x7) << 28) /* ADD_LAT */
703 | ((cpo & 0x1f) << 23) /* CPO */
704 | ((wr_lat & 0x7) << 19) /* WR_LAT */
705 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
706 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
707 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
708 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
711 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
715 * Determine the Mode Register Set.
717 * This is nominally part specific, but it appears to be
718 * consistent for all DDR I devices, and for all DDR II devices.
720 * caslat must be programmed
721 * burst length is always 4
722 * burst type is sequential
725 * operating mode is "normal"
734 * Table lookup from DDR I or II Device Operation Specs.
736 if (spd.mem_type == SPD_MEMTYPE_DDR) {
737 if (1 <= caslat && caslat <= 4) {
738 unsigned char mode_caslat_table[4] = {
739 0x5, /* 1.5 clocks */
740 0x2, /* 2.0 clocks */
741 0x6, /* 2.5 clocks */
744 mode_caslat = mode_caslat_table[caslat - 1];
746 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
747 "2.5 and 3.0 clocks are supported.\n");
752 if (2 <= caslat && caslat <= 5) {
753 mode_caslat = caslat;
755 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
756 "4.0 and 5.0 clocks are supported.\n");
762 * Encoded Burst Lenght of 4.
764 burst_len = 2; /* Fiat. */
766 if (spd.mem_type == SPD_MEMTYPE_DDR) {
767 twr_auto_clk = 0; /* Historical */
770 * Determine tCK max in picos. Grab tWR and convert to picos.
771 * Auto-precharge write recovery is:
772 * WR = roundup(tWR_ns/tCKmax_ns).
774 * Ponder: Is twr_auto_clk different than twr_clk?
776 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
777 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
782 * Mode Reg in bits 16 ~ 31,
783 * Extended Mode Reg 1 in bits 0 ~ 15.
785 mode_odt_enable = 0x0; /* Default disabled */
786 if (odt_wr_cfg || odt_rd_cfg) {
788 * Bits 6 and 2 in Extended MRS(1)
789 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
790 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
792 mode_odt_enable = 0x40; /* 150 Ohm */
797 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
798 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
799 | (twr_auto_clk << 9) /* Write Recovery Autopre */
800 | (mode_caslat << 4) /* caslat */
801 | (burst_len << 0) /* Burst length */
804 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
808 * Clear EMRS2 and EMRS3.
810 ddr->sdram_mode_2 = 0;
811 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
814 * Determine Refresh Rate.
816 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
819 * Set BSTOPRE to 0x100 for page mode
820 * If auto-charge is used, set BSTOPRE = 0
822 ddr->sdram_interval =
824 | (refresh_clk & 0x3fff) << 16
827 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
830 * Is this an ECC DDR chip?
831 * But don't mess with it if the DDR controller will init mem.
833 #ifdef CONFIG_DDR_ECC
834 if (spd.config == 0x02) {
835 #ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
836 ddr->err_disable = 0x0000000d;
838 ddr->err_sbe = 0x00ff0000;
841 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
842 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
843 #endif /* CONFIG_DDR_ECC */
845 asm("sync;isync;msync");
853 * When ODT is enabled, Chap 9 suggests asserting ODT to
854 * internal IOs only during reads.
857 if (odt_rd_cfg | odt_wr_cfg) {
858 odt_cfg = 0x2; /* ODT to IOs during reads */
862 * Try to use differential DQS with DDR II.
864 if (spd.mem_type == SPD_MEMTYPE_DDR) {
865 dqs_cfg = 0; /* No Differential DQS for DDR I */
867 dqs_cfg = 0x1; /* Differential DQS for DDR II */
870 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
872 * Use the DDR controller to auto initialize memory.
875 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
876 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
879 * Memory will be initialized via DMA, or not at all.
884 ddr->sdram_cfg_2 = (0
885 | (dqs_cfg << 26) /* Differential DQS */
886 | (odt_cfg << 21) /* ODT */
887 | (d_init << 4) /* D_INIT auto init DDR */
890 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
893 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
895 * Setup the clock control.
896 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
897 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
898 * 0110 3/4 cycle late
899 * 0111 7/8 cycle late
901 if (spd.mem_type == SPD_MEMTYPE_DDR)
904 #ifdef CONFIG_MPC8568
905 /* Empirally setting clk_adjust */
911 ddr->sdram_clk_cntl = (0
915 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
919 * Figure out the settings for the sdram_cfg register.
920 * Build up the entire register in 'sdram_cfg' before writing
921 * since the write into the register will actually enable the
922 * memory controller; all settings must be done before enabling.
924 * sdram_cfg[0] = 1 (ddr sdram logic enable)
925 * sdram_cfg[1] = 1 (self-refresh-enable)
926 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
930 sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
932 | (1 << 31) /* Enable */
933 | (1 << 30) /* Self refresh */
934 | (sdram_type << 24) /* SDRAM type */
938 * sdram_cfg[3] = RD_EN - registered DIMM enable
939 * A value of 0x26 indicates micron registered DIMMS (micron.com)
941 if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
942 sdram_cfg |= 0x10000000; /* RD_EN */
945 #if defined(CONFIG_DDR_ECC)
947 * If the user wanted ECC (enabled via sdram_cfg[2])
949 if (spd.config == 0x02) {
950 sdram_cfg |= 0x20000000; /* ECC_EN */
955 * REV1 uses 1T timing.
956 * REV2 may use 1T or 2T as configured by the user.
959 uint pvr = get_pvr();
961 if (pvr != PVR_85xx_REV1) {
962 #if defined(CONFIG_DDR_2T_TIMING)
964 * Enable 2T timing by setting sdram_cfg[16].
966 sdram_cfg |= 0x8000; /* 2T_EN */
972 * 200 painful micro-seconds must elapse between
973 * the DDR clock setup and the DDR config enable.
980 ddr->sdram_cfg = sdram_cfg;
982 asm("sync;isync;msync");
985 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
988 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
990 * Poll until memory is initialized.
991 * 512 Meg at 400 might hit this 200 times or so.
993 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1000 * Figure out memory size in Megabytes.
1002 memsize = n_ranks * rank_density / 0x100000;
1005 * Establish Local Access Window and TLB mappings for DDR memory.
1007 memsize = setup_laws_and_tlbs(memsize);
1012 return memsize * 1024 * 1024;
1017 * Setup Local Access Window and TLB1 mappings for the requested
1018 * amount of memory. Returns the amount of memory actually mapped
1019 * (usually the original request size), or 0 on error.
1023 setup_laws_and_tlbs(unsigned int memsize)
1025 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
1026 unsigned int tlb_size;
1027 unsigned int law_size;
1028 unsigned int ram_tlb_index;
1029 unsigned int ram_tlb_address;
1032 * Determine size of each TLB1 entry.
1037 tlb_size = BOOKE_PAGESZ_16M;
1041 tlb_size = BOOKE_PAGESZ_64M;
1045 tlb_size = BOOKE_PAGESZ_256M;
1049 if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
1050 tlb_size = BOOKE_PAGESZ_1G;
1052 tlb_size = BOOKE_PAGESZ_256M;
1055 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
1058 * The memory was not able to be mapped.
1059 * Default to a small size.
1061 tlb_size = BOOKE_PAGESZ_64M;
1067 * Configure DDR TLB1 entries.
1068 * Starting at TLB1 8, use no more than 8 TLB1 entries.
1071 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
1072 while (ram_tlb_address < (memsize * 1024 * 1024)
1073 && ram_tlb_index < 16) {
1074 mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
1075 mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
1076 mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
1077 mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
1078 (MAS3_SX|MAS3_SW|MAS3_SR)));
1079 asm volatile("isync;msync;tlbwe;isync");
1081 debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
1082 debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
1083 debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
1084 debug("DDR: MAS3=0x%08x\n",
1085 FSL_BOOKE_MAS3(ram_tlb_address, 0,
1086 (MAS3_SX|MAS3_SW|MAS3_SR)));
1088 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
1094 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1096 law_size = 19 + __ilog2(memsize);
1099 * Set up LAWBAR for all of DDR.
1101 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1102 ecm->lawar1 = (LAWAR_EN
1104 | (LAWAR_SIZE & law_size));
1105 debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
1106 debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
1109 * Confirm that the requested amount of memory was mapped.
1114 #endif /* CONFIG_SPD_EEPROM */
1117 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1120 * Initialize all of memory for ECC, then enable errors.
1124 ddr_enable_ecc(unsigned int dram_size)
1128 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
1132 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1133 if (((unsigned int)p & 0x1f) == 0) {
1134 ppcDcbz((unsigned long) p);
1136 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1137 if (((unsigned int)p & 0x1c) == 0x1c) {
1138 ppcDcbf((unsigned long) p);
1142 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1143 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1144 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1145 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1146 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1147 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1148 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1149 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1150 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1151 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
1153 for (i = 1; i < dram_size / 0x800000; i++) {
1154 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1158 * Enable errors for ECC.
1160 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1161 ddr->err_disable = 0x00000000;
1162 asm("sync;isync;msync");
1163 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1166 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */