2 * (C) Copyright 2003 Motorola Inc.
3 * Xianghua Xiao (X.Xiao@motorola.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 #ifdef CONFIG_SPD_EEPROM
40 #define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
42 long int spd_sdram(void) {
43 volatile immap_t *immap = (immap_t *)CFG_IMMR;
44 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
45 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
47 unsigned int memsize,tmp,tmp1,tmp2;
50 i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
52 if ( spd.nrows > 2 ) {
53 printf("DDR:Only two chip selects are supported on ADS.\n");
57 if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
58 printf("DDR:Row or Col number unsupported.\n");
62 ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
63 ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
65 DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
66 DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
67 if ( spd.nrows == 2 ) {
68 ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
69 ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
70 DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
71 DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
74 memsize = spd.nrows * (4 * spd.row_dens);
75 if( spd.mem_type == 0x07 ) {
76 printf("DDR module detected, total size:%dMB.\n",memsize);
78 printf("No DDR module found!\n");
84 tmp = 7; /* TLB size */
85 tmp1 = 1; /* TLB entry number */
86 tmp2 = 23; /* Local Access Window size */
119 printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
124 /* configure DDR TLB to TLB1 Entry 4,5 */
125 mtspr(MAS0, TLB1_MAS0(1,4,0));
126 mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
127 mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
128 mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
129 asm volatile("isync;msync;tlbwe;isync");
130 DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
131 DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
132 DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
133 & 0xfffff),0,0,0,0,0,0,0,0)));
134 DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
135 & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
138 mtspr(MAS0, TLB1_MAS0(1,5,0));
139 mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
140 mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
141 & 0xfffff),0,0,0,0,0,0,0,0));
142 mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
143 & 0xfffff),0,0,0,0,0,1,0,1,0,1));
144 asm volatile("isync;msync;tlbwe;isync");
145 DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
146 DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
147 DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
148 +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
149 DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
150 +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
153 #if defined(CONFIG_RAM_AS_FLASH)
154 ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
155 ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
156 DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
157 DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
159 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
160 ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
161 DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
162 DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
165 tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
166 DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
168 /* find the largest CAS */
169 if(spd.cas_lat & 0x40) {
171 } else if (spd.cas_lat & 0x20) {
173 } else if (spd.cas_lat & 0x10) {
175 } else if (spd.cas_lat & 0x08) {
177 } else if (spd.cas_lat & 0x04) {
179 } else if (spd.cas_lat & 0x02) {
181 } else if (spd.cas_lat & 0x01) {
184 printf("DDR:no valid CAS Latency information.\n");
188 tmp1 = get_bus_freq(0)/1000000;
189 if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
190 if(spd.clk_cycle3 == 0xa0) caslat -= 2;
191 else if(spd.clk_cycle2 == 0xa0) caslat--;
192 } else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
193 if(spd.clk_cycle3 == 0x75) caslat -= 2;
194 else if(spd.clk_cycle2 == 0x75) caslat--;
195 } else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
196 if(spd.clk_cycle3 == 0x60) caslat -= 2;
197 else if(spd.clk_cycle2 == 0x60) caslat--;
198 } else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
199 printf("DDR:platform frequency is not fit for DDR rate\n");
203 /* note: caslat must also be programmed into ddr->sdram_mode register */
204 /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
206 ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
207 ((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
208 ((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
209 ((caslat & 0x07)<< 16 ) | \
210 (((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
212 ((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
214 ddr->timing_cfg_1 = 0x37344321;
217 DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
219 /* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
220 #if defined(CONFIG_MPC85xx_REV1)
221 ddr->timing_cfg_2 = 0x00000800;
223 DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
225 /* only DDR I is supported, DDR I and II have different mode-register-set definition */
226 /* burst length is always 4 */
229 ddr->sdram_mode = 0x52; /* 1.5 */
232 ddr->sdram_mode = 0x22; /* 2.0 */
235 ddr->sdram_mode = 0x62; /* 2.5 */
238 ddr->sdram_mode = 0x32; /* 3.0 */
241 printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
244 DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
246 switch(spd.refresh) {
269 tmp = ns2clk(125000);
276 /* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
277 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
278 DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
280 /* is this an ECC DDR chip? */
281 #if defined(CONFIG_DDR_ECC)
282 if(spd.config == 0x02) {
283 ddr->err_disable = 0x0000000d;
284 ddr->err_sbe = 0x00ff0000;
286 DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
287 DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
289 asm("sync;isync;msync");
293 /* registered or unbuffered? */
294 #if defined(CONFIG_DDR_ECC)
295 ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
297 ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
298 ((spd.mod_attr == 0x26) ? 0x10000000:0x0));
299 asm("sync;isync;msync");
303 DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
305 return (memsize*1024*1024);
308 #endif /* CONFIG_SPD_EEPROM */