2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
31 #if defined(CONFIG_DDR_ECC)
32 extern void dma_init (void);
33 extern uint dma_check(void);
34 extern int dma_xfer (void *dest, uint count, void *src);
37 #ifdef CONFIG_SPD_EEPROM
40 #define CFG_READ_SPD i2c_read
44 * Convert picoseconds into clock cycles (rounding up if needed).
48 picos_to_clk(int picos)
52 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
53 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
61 banksize(unsigned char row_dens)
63 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
69 volatile immap_t *immap = (immap_t *)CFG_IMMR;
70 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
71 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
75 unsigned int tlb_size;
76 unsigned int law_size;
78 unsigned int ram_tlb_index;
79 unsigned int ram_tlb_address;
81 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
84 puts("DDR:Only two chip selects are supported on ADS.\n");
88 if (spd.nrow_addr < 12
91 || spd.ncol_addr > 11) {
92 puts("DDR:Row or Col number unsupported.\n");
96 ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
97 ddr->cs0_config = ( 1 << 31
98 | (spd.nrow_addr - 12) << 8
99 | (spd.ncol_addr - 8) );
101 debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
102 debug("cs0_config = 0x%08x\n",ddr->cs0_config);
104 if (spd.nrows == 2) {
105 ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
106 | ((banksize(spd.row_dens) >> 23) - 1) );
107 ddr->cs1_config = ( 1<<31
108 | (spd.nrow_addr-12) << 8
109 | (spd.ncol_addr-8) );
110 debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
111 debug("cs1_config = 0x%08x\n",ddr->cs1_config);
114 if (spd.mem_type != 0x07) {
115 puts("No DDR module found!\n");
120 * Figure out memory size in Megabytes.
122 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
125 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
127 law_size = 19 + __ilog2(memsize);
130 * Determine size of each TLB1 entry.
135 tlb_size = BOOKE_PAGESZ_16M;
139 tlb_size = BOOKE_PAGESZ_64M;
145 tlb_size = BOOKE_PAGESZ_256M;
148 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
154 * Configure DDR TLB1 entries.
155 * Starting at TLB1 8, use no more than 8 TLB1 entries.
158 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
159 while (ram_tlb_address < (memsize * 1024 * 1024)
160 && ram_tlb_index < 16) {
161 mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
162 mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
163 mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
164 0, 0, 0, 0, 0, 0, 0, 0));
165 mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
166 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
167 asm volatile("isync;msync;tlbwe;isync");
169 debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
170 debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
171 debug("DDR:MAS2=0x%08x\n",
172 TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
173 0, 0, 0, 0, 0, 0, 0, 0));
174 debug("DDR:MAS3=0x%08x\n",
175 TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
176 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
178 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
183 * Set up LAWBAR for all of DDR.
185 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
186 ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
187 debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
188 debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
191 * find the largest CAS
193 if(spd.cas_lat & 0x40) {
195 } else if (spd.cas_lat & 0x20) {
197 } else if (spd.cas_lat & 0x10) {
199 } else if (spd.cas_lat & 0x08) {
201 } else if (spd.cas_lat & 0x04) {
203 } else if (spd.cas_lat & 0x02) {
205 } else if (spd.cas_lat & 0x01) {
208 puts("DDR:no valid CAS Latency information.\n");
212 tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
213 + (spd.clk_cycle & 0x0f));
214 debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
216 tmp1 = get_bus_freq(0) / 1000000;
217 if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
218 /* 90~230 range, treated as DDR 200 */
219 if (spd.clk_cycle3 == 0xa0)
221 else if(spd.clk_cycle2 == 0xa0)
223 } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
224 /* 230-280 range, treated as DDR 266 */
225 if (spd.clk_cycle3 == 0x75)
227 else if (spd.clk_cycle2 == 0x75)
229 } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
230 /* 280~350 range, treated as DDR 333 */
231 if (spd.clk_cycle3 == 0x60)
233 else if (spd.clk_cycle2 == 0x60)
235 } else if (tmp1 < 90 || tmp1 >= 350) {
236 /* DDR rate out-of-range */
237 puts("DDR:platform frequency is not fit for DDR rate\n");
242 * note: caslat must also be programmed into ddr->sdram_mode
245 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
246 * use conservative value here.
249 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
250 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
251 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
252 ((caslat & 0x07) << 16 ) |
253 (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
255 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
257 ddr->timing_cfg_2 = 0x00000800;
259 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
260 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
263 * Only DDR I is supported
264 * DDR I and II have different mode-register-set definition
267 /* burst length is always 4 */
270 ddr->sdram_mode = 0x52; /* 1.5 */
273 ddr->sdram_mode = 0x22; /* 2.0 */
276 ddr->sdram_mode = 0x62; /* 2.5 */
279 ddr->sdram_mode = 0x32; /* 3.0 */
282 puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
285 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
287 switch(spd.refresh) {
290 tmp = picos_to_clk(15625000);
294 tmp = picos_to_clk(3900000);
298 tmp = picos_to_clk(7800000);
302 tmp = picos_to_clk(31300000);
306 tmp = picos_to_clk(62500000);
310 tmp = picos_to_clk(125000000);
318 * Set BSTOPRE to 0x100 for page mode
319 * If auto-charge is used, set BSTOPRE = 0
321 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
322 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
325 * Is this an ECC DDR chip?
327 #if defined(CONFIG_DDR_ECC)
328 if (spd.config == 0x02) {
329 ddr->err_disable = 0x0000000d;
330 ddr->err_sbe = 0x00ff0000;
332 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
333 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
335 asm("sync;isync;msync");
339 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
340 /* Setup the clock control (8555 and later)
341 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
342 * SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
344 ddr->sdram_clk_cntl = 0x83000000;
348 * Figure out the settings for the sdram_cfg register. Build up
349 * the entire register in 'tmp' before writing since the write into
350 * the register will actually enable the memory controller, and all
351 * settings must be done before enabling.
353 * sdram_cfg[0] = 1 (ddr sdram logic enable)
354 * sdram_cfg[1] = 1 (self-refresh-enable)
355 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
360 * sdram_cfg[3] = RD_EN - registered DIMM enable
361 * A value of 0x26 indicates micron registered DIMMS (micron.com)
363 if (spd.mod_attr == 0x26) {
367 #if defined(CONFIG_DDR_ECC)
369 * If the user wanted ECC (enabled via sdram_cfg[2])
371 if (spd.config == 0x02) {
377 * REV1 uses 1T timing.
378 * REV2 may use 1T or 2T as configured by the user.
381 uint pvr = get_pvr();
383 if (pvr != PVR_85xx_REV1) {
384 #if defined(CONFIG_DDR_2T_TIMING)
386 * Enable 2T timing by setting sdram_cfg[16].
393 ddr->sdram_cfg = tmp;
395 asm("sync;isync;msync");
398 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
400 return memsize * 1024 * 1024;
402 #endif /* CONFIG_SPD_EEPROM */
405 #if defined(CONFIG_DDR_ECC)
407 * Initialize all of memory for ECC, then enable errors.
410 ddr_enable_ecc(unsigned int dram_size)
414 volatile immap_t *immap = (immap_t *)CFG_IMMR;
415 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
419 for (*p = 0; p < (uint *)(8 * 1024); p++) {
420 if (((unsigned int)p & 0x1f) == 0) {
421 ppcDcbz((unsigned long) p);
423 *p = (unsigned int)0xdeadbeef;
424 if (((unsigned int)p & 0x1c) == 0x1c) {
425 ppcDcbf((unsigned long) p);
430 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
432 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
434 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
436 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
438 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
440 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
442 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
444 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
446 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
448 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
450 for (i = 1; i < dram_size / 0x800000; i++) {
451 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
455 * Enable errors for ECC.
457 ddr->err_disable = 0x00000000;
458 asm("sync;isync;msync");
460 #endif /* CONFIG_DDR_ECC */