2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
31 #ifdef CONFIG_SPD_EEPROM
34 #if defined(CONFIG_DDR_ECC)
35 extern void dma_init(void);
36 extern uint dma_check(void);
37 extern int dma_xfer(void *dest, uint count, void *src);
42 #define CFG_READ_SPD i2c_read
47 * Convert picoseconds into clock cycles (rounding up if needed).
51 picos_to_clk(int picos)
55 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
56 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
65 banksize(unsigned char row_dens)
67 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
74 volatile immap_t *immap = (immap_t *)CFG_IMMR;
75 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
76 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
80 unsigned int tlb_size;
81 unsigned int law_size;
83 unsigned int ram_tlb_index;
84 unsigned int ram_tlb_address;
86 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
89 puts("DDR:Only two chip selects are supported on ADS.\n");
93 if (spd.nrow_addr < 12
96 || spd.ncol_addr > 11) {
97 puts("DDR:Row or Col number unsupported.\n");
101 ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
102 ddr->cs0_config = ( 1 << 31
103 | (spd.nrow_addr - 12) << 8
104 | (spd.ncol_addr - 8) );
106 debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
107 debug("cs0_config = 0x%08x\n",ddr->cs0_config);
109 if (spd.nrows == 2) {
110 ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
111 | ((banksize(spd.row_dens) >> 23) - 1) );
112 ddr->cs1_config = ( 1<<31
113 | (spd.nrow_addr-12) << 8
114 | (spd.ncol_addr-8) );
115 debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
116 debug("cs1_config = 0x%08x\n",ddr->cs1_config);
119 if (spd.mem_type != 0x07) {
120 puts("No DDR module found!\n");
125 * Figure out memory size in Megabytes.
127 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
130 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
132 law_size = 19 + __ilog2(memsize);
135 * Determine size of each TLB1 entry.
140 tlb_size = BOOKE_PAGESZ_16M;
144 tlb_size = BOOKE_PAGESZ_64M;
150 tlb_size = BOOKE_PAGESZ_256M;
153 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
159 * Configure DDR TLB1 entries.
160 * Starting at TLB1 8, use no more than 8 TLB1 entries.
163 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
164 while (ram_tlb_address < (memsize * 1024 * 1024)
165 && ram_tlb_index < 16) {
166 mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
167 mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
168 mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
169 0, 0, 0, 0, 0, 0, 0, 0));
170 mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
171 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
172 asm volatile("isync;msync;tlbwe;isync");
174 debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
175 debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
176 debug("DDR:MAS2=0x%08x\n",
177 TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
178 0, 0, 0, 0, 0, 0, 0, 0));
179 debug("DDR:MAS3=0x%08x\n",
180 TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
181 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
183 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
188 * Set up LAWBAR for all of DDR.
190 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
191 ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
192 debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
193 debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
196 * find the largest CAS
198 if(spd.cas_lat & 0x40) {
200 } else if (spd.cas_lat & 0x20) {
202 } else if (spd.cas_lat & 0x10) {
204 } else if (spd.cas_lat & 0x08) {
206 } else if (spd.cas_lat & 0x04) {
208 } else if (spd.cas_lat & 0x02) {
210 } else if (spd.cas_lat & 0x01) {
213 puts("DDR:no valid CAS Latency information.\n");
217 tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
218 + (spd.clk_cycle & 0x0f));
219 debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
221 tmp1 = get_bus_freq(0) / 1000000;
222 if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
223 /* 90~230 range, treated as DDR 200 */
224 if (spd.clk_cycle3 == 0xa0)
226 else if(spd.clk_cycle2 == 0xa0)
228 } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
229 /* 230-280 range, treated as DDR 266 */
230 if (spd.clk_cycle3 == 0x75)
232 else if (spd.clk_cycle2 == 0x75)
234 } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
235 /* 280~350 range, treated as DDR 333 */
236 if (spd.clk_cycle3 == 0x60)
238 else if (spd.clk_cycle2 == 0x60)
240 } else if (tmp1 < 90 || tmp1 >= 350) {
241 /* DDR rate out-of-range */
242 puts("DDR:platform frequency is not fit for DDR rate\n");
247 * note: caslat must also be programmed into ddr->sdram_mode
250 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
251 * use conservative value here.
254 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
255 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
256 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
257 ((caslat & 0x07) << 16 ) |
258 (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
260 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
262 ddr->timing_cfg_2 = 0x00000800;
264 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
265 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
268 * Only DDR I is supported
269 * DDR I and II have different mode-register-set definition
272 /* burst length is always 4 */
275 ddr->sdram_mode = 0x52; /* 1.5 */
278 ddr->sdram_mode = 0x22; /* 2.0 */
281 ddr->sdram_mode = 0x62; /* 2.5 */
284 ddr->sdram_mode = 0x32; /* 3.0 */
287 puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
290 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
292 switch(spd.refresh) {
295 tmp = picos_to_clk(15625000);
299 tmp = picos_to_clk(3900000);
303 tmp = picos_to_clk(7800000);
307 tmp = picos_to_clk(31300000);
311 tmp = picos_to_clk(62500000);
315 tmp = picos_to_clk(125000000);
323 * Set BSTOPRE to 0x100 for page mode
324 * If auto-charge is used, set BSTOPRE = 0
326 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
327 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
330 * Is this an ECC DDR chip?
332 #if defined(CONFIG_DDR_ECC)
333 if (spd.config == 0x02) {
334 ddr->err_disable = 0x0000000d;
335 ddr->err_sbe = 0x00ff0000;
337 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
338 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
340 asm("sync;isync;msync");
344 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
345 /* Setup the clock control (8555 and later)
346 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
347 * SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
349 ddr->sdram_clk_cntl = 0x83000000;
353 * Figure out the settings for the sdram_cfg register. Build up
354 * the entire register in 'tmp' before writing since the write into
355 * the register will actually enable the memory controller, and all
356 * settings must be done before enabling.
358 * sdram_cfg[0] = 1 (ddr sdram logic enable)
359 * sdram_cfg[1] = 1 (self-refresh-enable)
360 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
365 * sdram_cfg[3] = RD_EN - registered DIMM enable
366 * A value of 0x26 indicates micron registered DIMMS (micron.com)
368 if (spd.mod_attr == 0x26) {
372 #if defined(CONFIG_DDR_ECC)
374 * If the user wanted ECC (enabled via sdram_cfg[2])
376 if (spd.config == 0x02) {
382 * REV1 uses 1T timing.
383 * REV2 may use 1T or 2T as configured by the user.
386 uint pvr = get_pvr();
388 if (pvr != PVR_85xx_REV1) {
389 #if defined(CONFIG_DDR_2T_TIMING)
391 * Enable 2T timing by setting sdram_cfg[16].
398 ddr->sdram_cfg = tmp;
400 asm("sync;isync;msync");
403 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
405 return memsize * 1024 * 1024;
408 #endif /* CONFIG_SPD_EEPROM */
411 #if defined(CONFIG_DDR_ECC)
413 * Initialize all of memory for ECC, then enable errors.
417 ddr_enable_ecc(unsigned int dram_size)
421 volatile immap_t *immap = (immap_t *)CFG_IMMR;
422 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
426 for (*p = 0; p < (uint *)(8 * 1024); p++) {
427 if (((unsigned int)p & 0x1f) == 0) {
428 ppcDcbz((unsigned long) p);
430 *p = (unsigned int)0xdeadbeef;
431 if (((unsigned int)p & 0x1c) == 0x1c) {
432 ppcDcbf((unsigned long) p);
437 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
439 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
441 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
443 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
445 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
447 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
449 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
451 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
453 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
455 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
457 for (i = 1; i < dram_size / 0x800000; i++) {
458 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
462 * Enable errors for ECC.
464 ddr->err_disable = 0x00000000;
465 asm("sync;isync;msync");
468 #endif /* CONFIG_DDR_ECC */