2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
44 static unsigned int setup_laws_and_tlbs(unsigned int memsize);
48 * Convert picoseconds into clock cycles (rounding up if needed).
52 picos_to_clk(int picos)
56 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
57 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
66 * Calculate the Density of each Physical Rank.
67 * Returned size is in bytes.
69 * Study these table from Byte 31 of JEDEC SPD Spec.
83 * Reorder Table to be linear by stripping the bottom
84 * 2 or 5 bits off and shifting them up to the top.
88 compute_banksize(unsigned int mem_type, unsigned char row_dens)
92 if (mem_type == SPD_MEMTYPE_DDR) {
93 /* Bottom 2 bits up to the top. */
94 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
95 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
97 /* Bottom 5 bits up to the top. */
98 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
99 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
106 * Convert a two-nibble BCD value into a cycle time.
107 * While the spec calls for nano-seconds, picos are returned.
109 * This implements the tables for bytes 9, 23 and 25 for both
110 * DDR I and II. No allowance for distinguishing the invalid
111 * fields absent for DDR I yet present in DDR II is made.
112 * (That is, cycle times of .25, .33, .66 and .75 ns are
113 * allowed for both DDR II and I.)
117 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
120 * Table look up the lower nibble, allow DDR I & II.
122 unsigned int tenths_ps[16] = {
134 330, /* FIXME: Is 333 better/valid? */
135 660, /* FIXME: Is 667 better/valid? */
141 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
142 unsigned int tenth_ns = spd_val & 0x0F;
143 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
152 volatile immap_t *immap = (immap_t *)CFG_IMMR;
153 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
154 volatile ccsr_gur_t *gur = &immap->im_gur;
156 unsigned int n_ranks;
157 unsigned int rank_density;
158 unsigned int odt_rd_cfg, odt_wr_cfg;
159 unsigned int odt_cfg, mode_odt_enable;
160 unsigned int dqs_cfg;
161 unsigned char twr_clk, twtr_clk, twr_auto_clk;
162 unsigned int tCKmin_ps, tCKmax_ps;
163 unsigned int max_data_rate, effective_data_rate;
164 unsigned int busfreq;
166 unsigned int memsize;
167 unsigned char caslat, caslat_ctrl;
168 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
169 unsigned int trcd_clk;
170 unsigned int trtp_clk;
171 unsigned char cke_min_clk;
172 unsigned char add_lat;
173 unsigned char wr_lat;
174 unsigned char wr_data_delay;
175 unsigned char four_act;
177 unsigned char burst_len;
178 unsigned int mode_caslat;
179 unsigned char sdram_type;
180 unsigned char d_init;
183 * Read SPD information.
185 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
188 * Check for supported memory module types.
190 if (spd.mem_type != SPD_MEMTYPE_DDR &&
191 spd.mem_type != SPD_MEMTYPE_DDR2) {
192 printf("Unable to locate DDR I or DDR II module.\n"
193 " Fundamental memory type is 0x%0x\n",
199 * These test gloss over DDR I and II differences in interpretation
200 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
201 * are not supported on DDR I; and not encoded on DDR II.
203 * Also note that the 8548 controller can support:
206 * 8 <= ncol <= 11 (still, for DDR)
207 * 6 <= ncol <= 9 (for FCRAM)
209 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
210 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
214 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
215 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
221 * Determine the number of physical banks controlled by
222 * different Chip Select signals. This is not quite the
223 * same as the number of DIMM modules on the board. Feh.
225 if (spd.mem_type == SPD_MEMTYPE_DDR) {
228 n_ranks = (spd.nrows & 0x7) + 1;
231 debug("DDR: number of ranks = %d\n", n_ranks);
234 printf("DDR: Only 2 chip selects are supported: %d\n",
240 * Adjust DDR II IO voltage biasing. It just makes it work.
242 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
244 | 0x80000000 /* Enable */
245 | 0x10000000 /* VSEL to 1.8V */
250 * Determine the size of each Rank in bytes.
252 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
256 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
258 ddr->cs0_bnds = (rank_density >> 24) - 1;
261 * ODT configuration recommendation from DDR Controller Chapter.
263 odt_rd_cfg = 0; /* Never assert ODT */
264 odt_wr_cfg = 0; /* Never assert ODT */
265 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
266 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
268 /* FIXME: How to determine the number of dimm modules? */
269 if (n_dimm_modules == 2) {
270 odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
275 ddr->cs0_config = ( 1 << 31
278 | (spd.nrow_addr - 12) << 8
279 | (spd.ncol_addr - 8) );
281 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
282 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
286 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
288 ddr->cs1_bnds = ( (rank_density >> 8)
289 | ((rank_density >> (24 - 1)) - 1) );
290 ddr->cs1_config = ( 1<<31
293 | (spd.nrow_addr - 12) << 8
294 | (spd.ncol_addr - 8) );
295 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
296 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
301 * Find the largest CAS by locating the highest 1 bit
302 * in the spd.cas_lat field. Translate it to a DDR
303 * controller field value:
305 * CAS Lat DDR I DDR II Ctrl
306 * Clocks SPD Bit SPD Bit Value
307 * ------- ------- ------- -----
318 caslat = __ilog2(spd.cas_lat);
319 if ((spd.mem_type == SPD_MEMTYPE_DDR)
321 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
324 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
325 && (caslat < 2 || caslat > 5)) {
326 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
330 debug("DDR: caslat SPD bit is %d\n", caslat);
333 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
334 * The SPD clk_cycle field (tCKmin) is measured in tenths of
335 * nanoseconds and represented as BCD.
337 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
338 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
341 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
343 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
344 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
348 * Adjust the CAS Latency to allow for bus speeds that
349 * are slower than the DDR module.
351 busfreq = get_bus_freq(0) / 1000000; /* MHz */
353 effective_data_rate = max_data_rate;
355 /* DDR rate out-of-range */
356 puts("DDR: platform frequency is not fit for DDR rate\n");
359 } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
361 * busfreq 90~230 range, treated as DDR 200.
363 effective_data_rate = 200;
364 if (spd.clk_cycle3 == 0xa0) /* 10 ns */
366 else if (spd.clk_cycle2 == 0xa0)
369 } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
371 * busfreq 230~280 range, treated as DDR 266.
373 effective_data_rate = 266;
374 if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
376 else if (spd.clk_cycle2 == 0x75)
379 } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
381 * busfreq 280~350 range, treated as DDR 333.
383 effective_data_rate = 333;
384 if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
386 else if (spd.clk_cycle2 == 0x60)
389 } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
391 * busfreq 350~460 range, treated as DDR 400.
393 effective_data_rate = 400;
394 if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
396 else if (spd.clk_cycle2 == 0x50)
399 } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
401 * busfreq 460~560 range, treated as DDR 533.
403 effective_data_rate = 533;
404 if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
406 else if (spd.clk_cycle2 == 0x3D)
409 } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
411 * busfreq 560~700 range, treated as DDR 667.
413 effective_data_rate = 667;
414 if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
416 else if (spd.clk_cycle2 == 0x30)
419 } else if (700 <= busfreq) {
421 * DDR rate out-of-range
423 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
424 busfreq, max_data_rate);
430 * Convert caslat clocks to DDR controller value.
431 * Force caslat_ctrl to be DDR Controller field-sized.
433 if (spd.mem_type == SPD_MEMTYPE_DDR) {
434 caslat_ctrl = (caslat + 1) & 0x07;
436 caslat_ctrl = (2 * caslat - 1) & 0x0f;
439 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
440 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
441 caslat, caslat_ctrl);
445 * Avoid writing for DDR I. The new PQ38 DDR controller
446 * dreams up non-zero default values to be backwards compatible.
448 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
449 unsigned char taxpd_clk = 8; /* By the book. */
450 unsigned char tmrd_clk = 2; /* By the book. */
451 unsigned char act_pd_exit = 2; /* Empirical? */
452 unsigned char pre_pd_exit = 6; /* Empirical? */
454 ddr->timing_cfg_0 = (0
455 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
456 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
457 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
458 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
461 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
463 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
468 * Force extra cycles with 0xaa bits.
469 * Incidentally supply the dreamt-up backwards compat value!
471 ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
472 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
473 debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
479 * Some Timing Config 1 values now.
480 * Sneak Extended Refresh Recovery in here too.
484 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
485 * use conservative value.
486 * For DDR II, they are bytes 36 and 37, in quarter nanos.
489 if (spd.mem_type == SPD_MEMTYPE_DDR) {
490 twr_clk = 3; /* Clocks */
491 twtr_clk = 1; /* Clocks */
493 twr_clk = picos_to_clk(spd.twr * 250);
494 twtr_clk = picos_to_clk(spd.twtr * 250);
498 * Calculate Trfc, in picos.
499 * DDR I: Byte 42 straight up in ns.
500 * DDR II: Byte 40 and 42 swizzled some, in ns.
502 if (spd.mem_type == SPD_MEMTYPE_DDR) {
503 trfc = spd.trfc * 1000; /* up to ps */
505 unsigned int byte40_table_ps[8] = {
516 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
517 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
519 trfc_clk = picos_to_clk(trfc);
522 * Trcd, Byte 29, from quarter nanos to ps and clocks.
524 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
527 * Convert trfc_clk to DDR controller fields. DDR I should
528 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
529 * 8548 controller has an extended REFREC field of three bits.
530 * The controller automatically adds 8 clocks to this value,
531 * so preadjust it down 8 first before splitting it up.
533 trfc_low = (trfc_clk - 8) & 0xf;
534 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
537 * Sneak in some Extended Refresh Recovery.
539 ddr->ext_refrec = (trfc_high << 16);
540 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
544 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
545 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
546 | (trcd_clk << 20) /* ACTTORW */
547 | (caslat_ctrl << 16) /* CASLAT */
548 | (trfc_low << 12) /* REFEC */
549 | ((twr_clk & 0x07) << 8) /* WRRREC */
550 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
551 | ((twtr_clk & 0x07) << 0) /* WRTORD */
554 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
565 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
566 * which comes from Trcd, and also note that:
567 * add_lat + caslat must be >= 4
570 if (spd.mem_type == SPD_MEMTYPE_DDR2
571 && (odt_wr_cfg || odt_rd_cfg)
573 add_lat = 4 - caslat;
574 if (add_lat > trcd_clk) {
575 add_lat = trcd_clk - 1;
581 * Historically 0x2 == 4/8 clock delay.
582 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
589 * Minimum CKE Pulse Width.
590 * Four Activate Window
592 if (spd.mem_type == SPD_MEMTYPE_DDR) {
594 * This is a lie. It should really be 1, but if it is
595 * set to 1, bits overlap into the old controller's
596 * otherwise unused ACSM field. If we leave it 0, then
597 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
601 trtp_clk = 2; /* By the book. */
602 cke_min_clk = 1; /* By the book. */
603 four_act = 1; /* By the book. */
608 /* Convert SPD value from quarter nanos to picos. */
609 trtp_clk = picos_to_clk(spd.trtp * 250);
611 cke_min_clk = 3; /* By the book. */
612 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
616 * Empirically set ~MCAS-to-preamble override for DDR 2.
617 * Your milage will vary.
620 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
621 if (effective_data_rate == 266 || effective_data_rate == 333) {
622 cpo = 0x7; /* READ_LAT + 5/4 */
623 } else if (effective_data_rate == 400) {
624 cpo = 0x9; /* READ_LAT + 7/4 */
626 /* Pure speculation */
631 ddr->timing_cfg_2 = (0
632 | ((add_lat & 0x7) << 28) /* ADD_LAT */
633 | ((cpo & 0x1f) << 23) /* CPO */
634 | ((wr_lat & 0x7) << 19) /* WR_LAT */
635 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
636 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
637 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
638 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
641 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
645 * Determine the Mode Register Set.
647 * This is nominally part specific, but it appears to be
648 * consistent for all DDR I devices, and for all DDR II devices.
650 * caslat must be programmed
651 * burst length is always 4
652 * burst type is sequential
655 * operating mode is "normal"
664 * Table lookup from DDR I or II Device Operation Specs.
666 if (spd.mem_type == SPD_MEMTYPE_DDR) {
667 if (1 <= caslat && caslat <= 4) {
668 unsigned char mode_caslat_table[4] = {
669 0x5, /* 1.5 clocks */
670 0x2, /* 2.0 clocks */
671 0x6, /* 2.5 clocks */
674 mode_caslat = mode_caslat_table[caslat - 1];
676 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
677 "2.5 and 3.0 clocks are supported.\n");
682 if (2 <= caslat && caslat <= 5) {
683 mode_caslat = caslat;
685 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
686 "4.0 and 5.0 clocks are supported.\n");
692 * Encoded Burst Lenght of 4.
694 burst_len = 2; /* Fiat. */
696 if (spd.mem_type == SPD_MEMTYPE_DDR) {
697 twr_auto_clk = 0; /* Historical */
700 * Determine tCK max in picos. Grab tWR and convert to picos.
701 * Auto-precharge write recovery is:
702 * WR = roundup(tWR_ns/tCKmax_ns).
704 * Ponder: Is twr_auto_clk different than twr_clk?
706 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
707 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
712 * Mode Reg in bits 16 ~ 31,
713 * Extended Mode Reg 1 in bits 0 ~ 15.
715 mode_odt_enable = 0x0; /* Default disabled */
716 if (odt_wr_cfg || odt_rd_cfg) {
718 * Bits 6 and 2 in Extended MRS(1)
719 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
720 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
722 mode_odt_enable = 0x40; /* 150 Ohm */
727 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
728 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
729 | (twr_auto_clk << 9) /* Write Recovery Autopre */
730 | (mode_caslat << 4) /* caslat */
731 | (burst_len << 0) /* Burst length */
734 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
738 * Clear EMRS2 and EMRS3.
740 ddr->sdram_mode_2 = 0;
741 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
745 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
746 * Table from SPD Spec, Byte 12, converted to picoseconds and
747 * filled in with "default" normal values.
750 unsigned int refresh_clk;
751 unsigned int refresh_time_ns[8] = {
752 15625000, /* 0 Normal 1.00x */
753 3900000, /* 1 Reduced .25x */
754 7800000, /* 2 Extended .50x */
755 31300000, /* 3 Extended 2.00x */
756 62500000, /* 4 Extended 4.00x */
757 125000000, /* 5 Extended 8.00x */
758 15625000, /* 6 Normal 1.00x filler */
759 15625000, /* 7 Normal 1.00x filler */
762 refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
765 * Set BSTOPRE to 0x100 for page mode
766 * If auto-charge is used, set BSTOPRE = 0
768 ddr->sdram_interval =
770 | (refresh_clk & 0x3fff) << 16
773 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
777 * Is this an ECC DDR chip?
778 * But don't mess with it if the DDR controller will init mem.
780 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
781 if (spd.config == 0x02) {
782 ddr->err_disable = 0x0000000d;
783 ddr->err_sbe = 0x00ff0000;
785 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
786 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
789 asm("sync;isync;msync");
797 * When ODT is enabled, Chap 9 suggests asserting ODT to
798 * internal IOs only during reads.
801 if (odt_rd_cfg | odt_wr_cfg) {
802 odt_cfg = 0x2; /* ODT to IOs during reads */
806 * Try to use differential DQS with DDR II.
808 if (spd.mem_type == SPD_MEMTYPE_DDR) {
809 dqs_cfg = 0; /* No Differential DQS for DDR I */
811 dqs_cfg = 0x1; /* Differential DQS for DDR II */
814 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
816 * Use the DDR controller to auto initialize memory.
819 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
820 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
823 * Memory will be initialized via DMA, or not at all.
828 ddr->sdram_cfg_2 = (0
829 | (dqs_cfg << 26) /* Differential DQS */
830 | (odt_cfg << 21) /* ODT */
831 | (d_init << 4) /* D_INIT auto init DDR */
834 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
837 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
839 unsigned char clk_adjust;
842 * Setup the clock control.
843 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
844 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
845 * 0110 3/4 cycle late
846 * 0111 7/8 cycle late
848 if (spd.mem_type == SPD_MEMTYPE_DDR) {
854 ddr->sdram_clk_cntl = (0
858 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
863 * Figure out the settings for the sdram_cfg register.
864 * Build up the entire register in 'sdram_cfg' before writing
865 * since the write into the register will actually enable the
866 * memory controller; all settings must be done before enabling.
868 * sdram_cfg[0] = 1 (ddr sdram logic enable)
869 * sdram_cfg[1] = 1 (self-refresh-enable)
870 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
874 sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
876 | (1 << 31) /* Enable */
877 | (1 << 30) /* Self refresh */
878 | (sdram_type << 24) /* SDRAM type */
882 * sdram_cfg[3] = RD_EN - registered DIMM enable
883 * A value of 0x26 indicates micron registered DIMMS (micron.com)
885 if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
886 sdram_cfg |= 0x10000000; /* RD_EN */
889 #if defined(CONFIG_DDR_ECC)
891 * If the user wanted ECC (enabled via sdram_cfg[2])
893 if (spd.config == 0x02) {
894 sdram_cfg |= 0x20000000; /* ECC_EN */
899 * REV1 uses 1T timing.
900 * REV2 may use 1T or 2T as configured by the user.
903 uint pvr = get_pvr();
905 if (pvr != PVR_85xx_REV1) {
906 #if defined(CONFIG_DDR_2T_TIMING)
908 * Enable 2T timing by setting sdram_cfg[16].
910 sdram_cfg |= 0x8000; /* 2T_EN */
916 * 200 painful micro-seconds must elapse between
917 * the DDR clock setup and the DDR config enable.
924 ddr->sdram_cfg = sdram_cfg;
926 asm("sync;isync;msync");
929 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
932 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
934 * Poll until memory is initialized.
935 * 512 Meg at 400 might hit this 200 times or so.
937 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
944 * Figure out memory size in Megabytes.
946 memsize = n_ranks * rank_density / 0x100000;
949 * Establish Local Access Window and TLB mappings for DDR memory.
951 memsize = setup_laws_and_tlbs(memsize);
956 return memsize * 1024 * 1024;
961 * Setup Local Access Window and TLB1 mappings for the requested
962 * amount of memory. Returns the amount of memory actually mapped
963 * (usually the original request size), or 0 on error.
967 setup_laws_and_tlbs(unsigned int memsize)
969 volatile immap_t *immap = (immap_t *)CFG_IMMR;
970 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
971 unsigned int tlb_size;
972 unsigned int law_size;
973 unsigned int ram_tlb_index;
974 unsigned int ram_tlb_address;
977 * Determine size of each TLB1 entry.
982 tlb_size = BOOKE_PAGESZ_16M;
986 tlb_size = BOOKE_PAGESZ_64M;
992 tlb_size = BOOKE_PAGESZ_256M;
995 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
998 * The memory was not able to be mapped.
1005 * Configure DDR TLB1 entries.
1006 * Starting at TLB1 8, use no more than 8 TLB1 entries.
1009 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
1010 while (ram_tlb_address < (memsize * 1024 * 1024)
1011 && ram_tlb_index < 16) {
1012 mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
1013 mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
1014 mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
1015 0, 0, 0, 0, 0, 0, 0, 0));
1016 mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
1017 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
1018 asm volatile("isync;msync;tlbwe;isync");
1020 debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
1021 debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
1022 debug("DDR: MAS2=0x%08x\n",
1023 TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
1024 0, 0, 0, 0, 0, 0, 0, 0));
1025 debug("DDR: MAS3=0x%08x\n",
1026 TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
1027 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
1029 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
1035 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1037 law_size = 19 + __ilog2(memsize);
1040 * Set up LAWBAR for all of DDR.
1042 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1043 ecm->lawar1 = (LAWAR_EN
1045 | (LAWAR_SIZE & law_size));
1046 debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
1047 debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
1050 * Confirm that the requested amount of memory was mapped.
1055 #endif /* CONFIG_SPD_EEPROM */
1058 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1061 * Initialize all of memory for ECC, then enable errors.
1065 ddr_enable_ecc(unsigned int dram_size)
1069 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1070 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
1074 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1075 if (((unsigned int)p & 0x1f) == 0) {
1076 ppcDcbz((unsigned long) p);
1078 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1079 if (((unsigned int)p & 0x1c) == 0x1c) {
1080 ppcDcbf((unsigned long) p);
1085 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
1087 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
1089 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
1091 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
1093 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
1095 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
1097 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
1099 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
1101 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
1103 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
1105 for (i = 1; i < dram_size / 0x800000; i++) {
1106 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1110 * Enable errors for ECC.
1112 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1113 ddr->err_disable = 0x00000000;
1114 asm("sync;isync;msync");
1115 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1118 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */