2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30 #include <ppc_asm.tmpl>
33 #include <asm/cache.h>
36 /* To boot secondary cpus, we need a place for them to start up.
37 * Normally, they start at 0xfffffffc, but that's usually the
38 * firmware, and we don't want to have to run the firmware again.
39 * Instead, the primary cpu will set the BPTR to point here to
40 * this page. We then set up the core, and head to
41 * start_secondary. Note that this means that the code below
42 * must never exceed 1023 instructions (the branch at the end
43 * would then be the 1024th).
45 .globl __secondary_start_page
47 __secondary_start_page:
48 /* First do some preliminary setup */
49 lis r3, HID0_EMCP@h /* enable machine check */
51 ori r3,r3,HID0_TBEN@l /* enable Timebase */
53 #ifdef CONFIG_PHYS_64BIT
54 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
59 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
63 /* Enable branch prediction */
72 /* Enable/invalidate the I-Cache */
74 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
78 /* Enable/invalidate the D-Cache */
80 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
86 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
88 /* get our PIR to figure out our table entry */
89 lis r3,toreset(__spin_table)@h
90 ori r3,r3,toreset(__spin_table)@l
92 /* r10 has the base address for the entry */
102 #ifdef CONFIG_BACKSIDE_L2_CACHE
103 /* Enable/invalidate the L2 cache */
109 andis. r1,r3,L2CSR0_L2FI@h
112 lis r3,CONFIG_SYS_INIT_L2CSR0@h
113 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
118 #define EPAPR_MAGIC (0x45504150)
119 #define ENTRY_ADDR_UPPER 0
120 #define ENTRY_ADDR_LOWER 4
121 #define ENTRY_R3_UPPER 8
122 #define ENTRY_R3_LOWER 12
123 #define ENTRY_RESV 16
125 #define ENTRY_R6_UPPER 24
126 #define ENTRY_R6_LOWER 28
127 #define ENTRY_SIZE 32
129 /* setup the entry */
132 stw r0,ENTRY_PIR(r10)
133 stw r3,ENTRY_ADDR_UPPER(r10)
134 stw r8,ENTRY_ADDR_LOWER(r10)
135 stw r3,ENTRY_R3_UPPER(r10)
136 stw r4,ENTRY_R3_LOWER(r10)
137 stw r3,ENTRY_R6_UPPER(r10)
138 stw r3,ENTRY_R6_LOWER(r10)
140 /* setup mapping for AS = 1, and jump there */
141 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
143 lis r11,(MAS1_VALID|MAS1_IPROT)@h
144 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
146 lis r11,(0xfffff000|MAS2_I)@h
147 ori r11,r11,(0xfffff000|MAS2_I)@l
149 lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
150 ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
158 ori r12,r13,MSR_IS|MSR_DS@l
164 /* spin waiting for addr */
166 lwz r4,ENTRY_ADDR_LOWER(r10)
171 /* get the upper bits of the addr */
172 lwz r11,ENTRY_ADDR_UPPER(r10)
174 /* setup branch addr */
177 /* mark the entry as released */
179 stw r8,ENTRY_ADDR_LOWER(r10)
181 /* mask by ~64M to setup our tlb we will jump to */
184 /* setup r3, r4, r5, r6, r7, r8, r9 */
185 lwz r3,ENTRY_R3_LOWER(r10)
188 lwz r6,ENTRY_R6_LOWER(r10)
189 lis r7,(64*1024*1024)@h
193 /* load up the pir */
194 lwz r0,ENTRY_PIR(r10)
197 stw r0,ENTRY_PIR(r10)
201 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
202 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
203 * second mapping that maps addr 1:1 for 64M, and then we jump to
206 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
208 lis r10,(MAS1_VALID|MAS1_IPROT)@h
209 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
211 /* WIMGE = 0b00000 for now */
213 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
215 #ifdef CONFIG_ENABLE_36BIT_PHYS
220 /* Now we have another mapping for this page, so we jump to that
226 .align L1_CACHE_SHIFT
229 .space CONFIG_MAX_CPUS*ENTRY_SIZE
231 /* Fill in the empty space. The actual reset vector is
232 * the last word of the page */
233 __secondary_start_code_end:
234 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
235 __secondary_reset_vector:
236 b __secondary_start_page