cpu/mpc85xx/pci.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright (C) 2003 Motorola Inc.
   4  * Xianghua Xiao (x.xiao@motorola.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * PCI Configuration space access support for MPC85xx PCI Bridge
  27  */
  28 #include <common.h>
  29 #include <asm/cpm_85xx.h>
  30 #include <pci.h>
  31
  32
  33 #if defined(CONFIG_PCI)
  34
  35 static struct pci_controller *pci_hose;
  36
  37 void
  38 pci_mpc85xx_init(struct pci_controller *board_hose)
  39 {
  40         u16 reg16;
  41         u32 dev;
  42
  43         volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
  44         volatile ccsr_pcix_t *pcix = &immap->im_pcix;
  45         volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
  46         volatile ccsr_gur_t *gur = &immap->im_gur;
  47         struct pci_controller * hose;
  48
  49         pci_hose = board_hose;
  50
  51         hose = &pci_hose[0];
  52
  53         hose->first_busno = 0;
  54         hose->last_busno = 0xff;
  55
  56         pci_setup_indirect(hose,
  57                            (CFG_IMMR+0x8000),
  58                            (CFG_IMMR+0x8004));
  59
  60         /*
  61          * Hose scan.
  62          */
  63         dev = PCI_BDF(hose->first_busno, 0, 0);
  64         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  65         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  66         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  67
  68         /*
  69          * Clear non-reserved bits in status register.
  70          */
  71         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  72
  73         if (!(gur->pordevsr & PORDEVSR_PCI)) {
  74                 /* PCI-X init */
  75                 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  76                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  77                 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  78         }
  79
  80         pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  81         pcix->potear1  = 0x00000000;
  82         pcix->powbar1  = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
  83         pcix->powbear1 = 0x00000000;
  84         pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  85                         POWAR_MEM_WRITE | POWAR_MEM_512M);
  86
  87         pcix->potar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  88         pcix->potear2  = 0x00000000;
  89         pcix->powbar2  = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
  90         pcix->powbear2 = 0x00000000;
  91         pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
  92                         POWAR_IO_WRITE | POWAR_IO_1M);
  93
  94         pcix->pitar1 = 0x00000000;
  95         pcix->piwbar1 = 0x00000000;
  96         pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  97                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  98
  99         pcix->powar3 = 0;
 100         pcix->powar4 = 0;
 101         pcix->piwar2 = 0;
 102         pcix->piwar3 = 0;
 103
 104         pci_set_region(hose->regions + 0,
 105                        CFG_PCI1_MEM_BASE,
 106                        CFG_PCI1_MEM_PHYS,
 107                        CFG_PCI1_MEM_SIZE,
 108                        PCI_REGION_MEM);
 109
 110         pci_set_region(hose->regions + 1,
 111                        CFG_PCI1_IO_BASE,
 112                        CFG_PCI1_IO_PHYS,
 113                        CFG_PCI1_IO_SIZE,
 114                        PCI_REGION_IO);
 115
 116         hose->region_count = 2;
 117
 118         pci_register_hose(hose);
 119
 120 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
 121         /*
 122          * This is a SW workaround for an apparent HW problem
 123          * in the PCI controller on the MPC85555/41 CDS boards.
 124          * The first config cycle must be to a valid, known
 125          * device on the PCI bus in order to trick the PCI
 126          * controller state machine into a known valid state.
 127          * Without this, the first config cycle has the chance
 128          * of hanging the controller permanently, just leaving
 129          * it in a semi-working state, or leaving it working.
 130          *
 131          * Pick on the Tundra, Device 17, to get it right.
 132          */
 133         {
 134                 u8 header_type;
 135
 136                 pci_hose_read_config_byte(hose,
 137                                           PCI_BDF(0,17,0),
 138                                           PCI_HEADER_TYPE,
 139                                           &header_type);
 140         }
 141 #endif
 142
 143         hose->last_busno = pci_hose_scan(hose);
 144
 145 #ifdef CONFIG_MPC85XX_PCI2
 146         hose = &pci_hose[1];
 147
 148         hose->first_busno = pci_hose[0].last_busno + 1;
 149         hose->last_busno = 0xff;
 150
 151         pci_setup_indirect(hose,
 152                            (CFG_IMMR+0x9000),
 153                            (CFG_IMMR+0x9004));
 154
 155         dev = PCI_BDF(hose->first_busno, 0, 0);
 156         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 157         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 158         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 159
 160         /*
 161          * Clear non-reserved bits in status register.
 162          */
 163         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 164
 165         pcix2->potar1   = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
 166         pcix2->potear1  = 0x00000000;
 167         pcix2->powbar1  = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
 168         pcix2->powbear1 = 0x00000000;
 169         pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
 170                         POWAR_MEM_WRITE | POWAR_MEM_512M);
 171
 172         pcix2->potar2  = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
 173         pcix2->potear2  = 0x00000000;
 174         pcix2->powbar2  = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
 175         pcix2->powbear2 = 0x00000000;
 176         pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
 177                         POWAR_IO_WRITE | POWAR_IO_1M);
 178
 179         pcix2->pitar1 = 0x00000000;
 180         pcix2->piwbar1 = 0x00000000;
 181         pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
 182                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
 183
 184         pcix2->powar3 = 0;
 185         pcix2->powar4 = 0;
 186         pcix2->piwar2 = 0;
 187         pcix2->piwar3 = 0;
 188
 189         pci_set_region(hose->regions + 0,
 190                        CFG_PCI2_MEM_BASE,
 191                        CFG_PCI2_MEM_PHYS,
 192                        CFG_PCI2_MEM_SIZE,
 193                        PCI_REGION_MEM);
 194
 195         pci_set_region(hose->regions + 1,
 196                        CFG_PCI2_IO_BASE,
 197                        CFG_PCI2_IO_PHYS,
 198                        CFG_PCI2_IO_SIZE,
 199                        PCI_REGION_IO);
 200
 201         hose->region_count = 2;
 202
 203         /*
 204          * Hose scan.
 205          */
 206         pci_register_hose(hose);
 207
 208         hose->last_busno = pci_hose_scan(hose);
 209 #endif
 210 }
 211
 212 #ifdef CONFIG_OF_FLAT_TREE
 213 void
 214 ft_pci_setup(void *blob, bd_t *bd)
 215 {
 216         u32 *p;
 217         int len;
 218
 219         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
 220         if (p != NULL) {
 221                 p[0] = pci_hose[0].first_busno;
 222                 p[1] = pci_hose[0].last_busno;
 223         }
 224
 225 #ifdef CONFIG_MPC85XX_PCI2
 226         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
 227         if (p != NULL) {
 228                 p[0] = pci_hose[1].first_busno;
 229                 p[1] = pci_hose[1].last_busno;
 230         }
 231 #endif
 232 }
 233 #endif /* CONFIG_OF_FLAT_TREE */
 234 #endif /* CONFIG_PCI */