2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
29 DECLARE_GLOBAL_DATA_PTR;
33 return mfspr(SPRN_PIR);
38 volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
39 out_be32(&pic->pir, 1 << nr);
40 (void)in_be32(&pic->pir);
41 out_be32(&pic->pir, 0x0);
46 int cpu_status(int nr)
48 u32 *table, id = get_my_id();
51 table = (u32 *)get_spin_addr();
52 printf("table base @ 0x%08x\n", table);
54 table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
55 printf("Running on cpu %d\n", id);
57 printf("table @ 0x%08x:\n", table);
58 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
59 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
60 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
61 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
67 static u8 boot_entry_map[4] = {
74 int cpu_release(int nr, int argc, char *argv[])
76 u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
79 if (nr == get_my_id()) {
80 printf("Invalid to release the boot core.\n\n");
85 printf("Invalid number of arguments to release.\n\n");
89 #ifdef CFG_64BIT_STRTOUL
90 boot_addr = simple_strtoull(argv[0], NULL, 16);
92 boot_addr = simple_strtoul(argv[0], NULL, 16);
95 /* handle pir, r3, r6 */
96 for (i = 1; i < 4; i++) {
97 if (argv[i][0] != '-') {
98 u8 entry = boot_entry_map[i];
99 val = simple_strtoul(argv[i], NULL, 16);
104 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
105 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
110 ulong get_spin_addr(void)
112 extern ulong __secondary_start_page;
113 extern ulong __spin_table;
116 (ulong)&__spin_table - (ulong)&__secondary_start_page;
122 static void pq3_mp_up(unsigned long bootpg)
124 u32 up, cpu_up_mask, whoami;
125 u32 *table = (u32 *)get_spin_addr();
127 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
128 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
129 volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
133 whoami = in_be32(&pic->whoami);
134 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
136 /* disable time base at the platform */
137 devdisr = in_be32(&gur->devdisr);
139 devdisr |= MPC85xx_DEVDISR_TB0;
141 devdisr |= MPC85xx_DEVDISR_TB1;
142 out_be32(&gur->devdisr, devdisr);
144 /* release the hounds */
145 up = ((1 << CONFIG_NR_CPUS) - 1);
146 bpcr = in_be32(&ecm->eebpcr);
148 out_be32(&ecm->eebpcr, bpcr);
149 asm("sync; isync; msync");
151 cpu_up_mask = 1 << whoami;
152 /* wait for everyone */
155 for (i = 1; i < CONFIG_NR_CPUS; i++) {
156 if (table[i * NUM_BOOT_ENTRY])
157 cpu_up_mask |= (1 << i);
160 if ((cpu_up_mask & up) == up)
167 /* enable time base at the platform */
169 devdisr |= MPC85xx_DEVDISR_TB1;
171 devdisr |= MPC85xx_DEVDISR_TB0;
172 out_be32(&gur->devdisr, devdisr);
176 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
177 out_be32(&gur->devdisr, devdisr);
182 extern ulong __secondary_start_page;
183 ulong fixup = (ulong)&__secondary_start_page;
186 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
187 if ((u64)gd->ram_size > 0xfffff000)
190 bootpg = gd->ram_size - 4096;
192 memcpy((void *)bootpg, (void *)fixup, 4096);
193 flush_cache(bootpg, 4096);