2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
34 return mfspr(SPRN_PIR);
39 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
40 out_be32(&pic->pir, 1 << nr);
41 /* the dummy read works around an errata on early 85xx MP PICs */
42 (void)in_be32(&pic->pir);
43 out_be32(&pic->pir, 0x0);
48 int cpu_status(int nr)
50 u32 *table, id = get_my_id();
53 table = (u32 *)get_spin_addr();
54 printf("table base @ 0x%p\n", table);
56 table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
57 printf("Running on cpu %d\n", id);
59 printf("table @ 0x%p\n", table);
60 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
61 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
62 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
63 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
69 static u8 boot_entry_map[4] = {
76 int cpu_release(int nr, int argc, char *argv[])
78 u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
81 if (nr == get_my_id()) {
82 printf("Invalid to release the boot core.\n\n");
87 printf("Invalid number of arguments to release.\n\n");
91 #ifdef CONFIG_SYS_64BIT_STRTOUL
92 boot_addr = simple_strtoull(argv[0], NULL, 16);
94 boot_addr = simple_strtoul(argv[0], NULL, 16);
97 /* handle pir, r3, r6 */
98 for (i = 1; i < 4; i++) {
99 if (argv[i][0] != '-') {
100 u8 entry = boot_entry_map[i];
101 val = simple_strtoul(argv[i], NULL, 16);
106 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
108 /* ensure all table updates complete before final address write */
111 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
116 u32 determine_mp_bootpg(void)
118 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
119 if ((u64)gd->ram_size > 0xfffff000)
122 return (gd->ram_size - 4096);
125 ulong get_spin_addr(void)
127 extern ulong __secondary_start_page;
128 extern ulong __spin_table;
131 (ulong)&__spin_table - (ulong)&__secondary_start_page;
137 static void pq3_mp_up(unsigned long bootpg)
139 u32 up, cpu_up_mask, whoami;
140 u32 *table = (u32 *)get_spin_addr();
142 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
143 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
144 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
148 whoami = in_be32(&pic->whoami);
149 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
151 /* disable time base at the platform */
152 devdisr = in_be32(&gur->devdisr);
154 devdisr |= MPC85xx_DEVDISR_TB0;
156 devdisr |= MPC85xx_DEVDISR_TB1;
157 out_be32(&gur->devdisr, devdisr);
159 /* release the hounds */
160 up = ((1 << CONFIG_NUM_CPUS) - 1);
161 bpcr = in_be32(&ecm->eebpcr);
163 out_be32(&ecm->eebpcr, bpcr);
164 asm("sync; isync; msync");
166 cpu_up_mask = 1 << whoami;
167 /* wait for everyone */
170 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
171 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
172 cpu_up_mask |= (1 << i);
175 if ((cpu_up_mask & up) == up)
183 printf("CPU up timeout. CPU up mask is %x should be %x\n",
186 /* enable time base at the platform */
188 devdisr |= MPC85xx_DEVDISR_TB1;
190 devdisr |= MPC85xx_DEVDISR_TB0;
191 out_be32(&gur->devdisr, devdisr);
195 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
196 out_be32(&gur->devdisr, devdisr);
199 void cpu_mp_lmb_reserve(struct lmb *lmb)
201 u32 bootpg = determine_mp_bootpg();
203 lmb_reserve(lmb, bootpg, 4096);
208 extern ulong __secondary_start_page;
209 ulong fixup = (ulong)&__secondary_start_page;
210 u32 bootpg = determine_mp_bootpg();
212 memcpy((void *)bootpg, (void *)fixup, 4096);
213 flush_cache(bootpg, 4096);