2 * Copyright 2007 Freescale Semiconductor.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 DECLARE_GLOBAL_DATA_PTR;
39 static void config_8560_ioports (volatile immap_t * immr)
43 for (portnum = 0; portnum < 4; portnum++) {
50 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
51 iop_conf_t *eiopc = iopc + 32;
56 * index 0 refers to pin 31,
57 * index 31 refers to pin 0
59 while (iopc < eiopc) {
79 volatile ioport_t *iop = ioport_addr (immr, portnum);
83 * the (somewhat confused) paragraph at the
84 * bottom of page 35-5 warns that there might
85 * be "unknown behaviour" when programming
86 * PSORx and PDIRx, if PPARx = 1, so I
87 * decided this meant I had to disable the
88 * dedicated function first, and enable it
92 iop->psor = (iop->psor & tpmsk) | psor;
93 iop->podr = (iop->podr & tpmsk) | podr;
94 iop->pdat = (iop->pdat & tpmsk) | pdat;
95 iop->pdir = (iop->pdir & tpmsk) | pdir;
103 * Breathe some life into the CPU...
105 * Set up the memory map
106 * initialize a bunch of registers
109 void cpu_init_f (void)
111 volatile immap_t *immap = (immap_t *)CFG_IMMR;
112 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
113 extern void m8560_cpm_reset (void);
115 /* Pointer is writable since we allocated a register for it */
116 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
118 /* Clear initial global data */
119 memset ((void *) gd, 0, sizeof (gd_t));
123 config_8560_ioports(immap);
126 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
127 * addresses - these have to be modified later when FLASH size
128 * has been determined
130 #if defined(CFG_OR0_REMAP)
131 memctl->or0 = CFG_OR0_REMAP;
133 #if defined(CFG_OR1_REMAP)
134 memctl->or1 = CFG_OR1_REMAP;
137 /* now restrict to preliminary range */
138 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
139 if (! memctl->br1 & 1) {
140 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
141 memctl->br0 = CFG_BR0_PRELIM;
142 memctl->or0 = CFG_OR0_PRELIM;
145 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
146 memctl->or1 = CFG_OR1_PRELIM;
147 memctl->br1 = CFG_BR1_PRELIM;
151 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
152 memctl->or2 = CFG_OR2_PRELIM;
153 memctl->br2 = CFG_BR2_PRELIM;
156 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
157 memctl->or3 = CFG_OR3_PRELIM;
158 memctl->br3 = CFG_BR3_PRELIM;
161 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
162 memctl->or4 = CFG_OR4_PRELIM;
163 memctl->br4 = CFG_BR4_PRELIM;
166 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
167 memctl->or5 = CFG_OR5_PRELIM;
168 memctl->br5 = CFG_BR5_PRELIM;
171 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
172 memctl->or6 = CFG_OR6_PRELIM;
173 memctl->br6 = CFG_BR6_PRELIM;
176 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
177 memctl->or7 = CFG_OR7_PRELIM;
178 memctl->br7 = CFG_BR7_PRELIM;
181 #if defined(CONFIG_CPM2)
188 * Initialize L2 as cache.
190 * The newer 8548, etc, parts have twice as much cache, but
191 * use the same bit-encoding as the older 8555, etc, parts.
197 volatile immap_t *immap = (immap_t *)CFG_IMMR;
198 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
200 #ifdef CONFIG_CLEAR_LAW0
201 /* clear alternate boot location LAW (used for sdram, or ddr bank) */
205 #if defined(CONFIG_L2_CACHE)
206 volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
207 volatile uint cache_ctl;
215 cache_ctl = l2cache->l2ctl;
217 switch (cache_ctl & 0x30000000) {
219 if (ver == SVR_8548 || ver == SVR_8548_E ||
221 printf ("L2 cache 512KB:");
222 /* set L2E=1, L2I=1, & L2SRAM=0 */
223 cache_ctl = 0xc0000000;
225 printf ("L2 cache 256KB:");
226 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
227 cache_ctl = 0xc8000000;
231 printf ("L2 cache 256KB:");
232 if (ver == SVR_8544 || ver == SVR_8544_E) {
233 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
239 printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
243 if (l2cache->l2ctl & 0x80000000) {
244 printf(" already enabled.");
245 l2srbar = l2cache->l2srbar0;
246 #ifdef CFG_INIT_L2_ADDR
247 if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
248 l2srbar = CFG_INIT_L2_ADDR;
249 l2cache->l2srbar0 = l2srbar;
250 printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
252 #endif /* CFG_INIT_L2_ADDR */
256 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
258 printf(" enabled\n");
261 printf("L2 cache: disabled\n");