2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 struct cpu_type cpu_type_list [] = {
39 CPU_TYPE_ENTRY(8533, 8533),
40 CPU_TYPE_ENTRY(8533, 8533_E),
41 CPU_TYPE_ENTRY(8536, 8536),
42 CPU_TYPE_ENTRY(8536, 8536_E),
43 CPU_TYPE_ENTRY(8540, 8540),
44 CPU_TYPE_ENTRY(8541, 8541),
45 CPU_TYPE_ENTRY(8541, 8541_E),
46 CPU_TYPE_ENTRY(8543, 8543),
47 CPU_TYPE_ENTRY(8543, 8543_E),
48 CPU_TYPE_ENTRY(8544, 8544),
49 CPU_TYPE_ENTRY(8544, 8544_E),
50 CPU_TYPE_ENTRY(8545, 8545),
51 CPU_TYPE_ENTRY(8545, 8545_E),
52 CPU_TYPE_ENTRY(8547, 8547_E),
53 CPU_TYPE_ENTRY(8548, 8548),
54 CPU_TYPE_ENTRY(8548, 8548_E),
55 CPU_TYPE_ENTRY(8555, 8555),
56 CPU_TYPE_ENTRY(8555, 8555_E),
57 CPU_TYPE_ENTRY(8560, 8560),
58 CPU_TYPE_ENTRY(8567, 8567),
59 CPU_TYPE_ENTRY(8567, 8567_E),
60 CPU_TYPE_ENTRY(8568, 8568),
61 CPU_TYPE_ENTRY(8568, 8568_E),
62 CPU_TYPE_ENTRY(8572, 8572),
63 CPU_TYPE_ENTRY(8572, 8572_E),
66 struct cpu_type *identify_cpu(u32 ver)
69 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
70 if (cpu_type_list[i].soc_ver == ver)
71 return &cpu_type_list[i];
79 uint lcrr; /* local bus clock ratio register */
80 uint clkdiv; /* clock divider portion of lcrr */
86 char buf1[32], buf2[32];
87 #ifdef CONFIG_DDR_CLK_FREQ
88 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
89 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
90 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
96 ver = SVR_SOC_VER(svr);
99 major &= 0x7; /* the msb of this nibble is a mfg code */
101 minor = SVR_MIN(svr);
103 #if (CONFIG_NUM_CPUS > 1)
104 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
105 printf("CPU%d: ", pic->whoami);
110 cpu = identify_cpu(ver);
114 if (IS_E_PROCESSOR(svr))
120 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
125 major = PVR_MAJ(pvr);
126 minor = PVR_MIN(pvr);
130 case PVR_FAM(PVR_85xx):
138 if (PVR_MEM(pvr) == 0x03)
141 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
143 get_sys_info(&sysinfo);
145 puts("Clock Configuration:\n");
146 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
147 printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
151 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
152 strmhz(buf1, sysinfo.freqDDRBus/2),
153 strmhz(buf2, sysinfo.freqDDRBus));
156 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
157 strmhz(buf1, sysinfo.freqDDRBus/2),
158 strmhz(buf2, sysinfo.freqDDRBus));
161 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
162 strmhz(buf1, sysinfo.freqDDRBus/2),
163 strmhz(buf2, sysinfo.freqDDRBus));
167 #if defined(CONFIG_SYS_LBC_LCRR)
168 lcrr = CONFIG_SYS_LBC_LCRR;
171 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
176 clkdiv = lcrr & 0x0f;
177 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
178 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
179 defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
181 * Yes, the entire PQ38 family use the same
182 * bit-representation for twice the clock divider values.
186 printf("LBC:%-4s MHz\n",
187 strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
189 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
193 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
196 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
202 /* ------------------------------------------------------------------------- */
204 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
208 unsigned long val, msr;
214 /* e500 v2 core has reset control register */
215 volatile unsigned int * rstcr;
216 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
217 *rstcr = 0x2; /* HRESET_REQ */
222 * Fallthrough if the code above failed
223 * Initiate hard reset in debug control register DBCR0
224 * Make sure MSR[DE] = 1
240 * Get timebase clock frequency
242 unsigned long get_tbclk (void)
244 return (gd->bus_clk + 4UL)/8UL;
248 #if defined(CONFIG_WATCHDOG)
252 int re_enable = disable_interrupts();
253 reset_85xx_watchdog();
254 if (re_enable) enable_interrupts();
258 reset_85xx_watchdog(void)
261 * Clear TSR(WIS) bit by writing 1
264 val = mfspr(SPRN_TSR);
266 mtspr(SPRN_TSR, val);
268 #endif /* CONFIG_WATCHDOG */
270 #if defined(CONFIG_DDR_ECC)
271 void dma_init(void) {
272 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
274 dma->satr0 = 0x02c40000;
275 dma->datr0 = 0x02c40000;
276 dma->sr0 = 0xfffffff; /* clear any errors */
277 asm("sync; isync; msync");
281 uint dma_check(void) {
282 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
283 volatile uint status = dma->sr0;
285 /* While the channel is busy, spin */
286 while((status & 4) == 4) {
290 /* clear MR0[CS] channel start bit */
291 dma->mr0 &= 0x00000001;
292 asm("sync;isync;msync");
295 printf ("DMA Error: status = %x\n", status);
300 int dma_xfer(void *dest, uint count, void *src) {
301 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
303 dma->dar0 = (uint) dest;
304 dma->sar0 = (uint) src;
306 dma->mr0 = 0xf000004;
307 asm("sync;isync;msync");
308 dma->mr0 = 0xf000005;
309 asm("sync;isync;msync");
315 * Configures a UPM. The function requires the respective MxMR to be set
316 * before calling this function. "size" is the number or entries, not a sizeof.
318 void upmconfig (uint upm, uint * table, uint size)
320 int i, mdr, mad, old_mad = 0;
322 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
323 volatile u32 *brp,*orp;
324 volatile u8* dummy = NULL;
330 upmmask = BR_MS_UPMA;
334 upmmask = BR_MS_UPMB;
338 upmmask = BR_MS_UPMC;
341 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
345 /* Find the address for the dummy write transaction */
346 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
347 i++, brp += 2, orp += 2) {
349 /* Look for a valid BR with selected UPM */
350 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
351 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
357 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
361 for (i = 0; i < size; i++) {
363 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
365 out_be32(&lbc->mdr, table[i]);
367 mdr = in_be32(&lbc->mdr);
369 *(volatile u8 *)dummy = 0;
372 mad = in_be32(mxmr) & MxMR_MAD_MSK;
373 } while (mad <= old_mad && !(!mad && i == (size-1)));
376 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
381 * Initializes on-chip ethernet controllers.
382 * to override, implement board_eth_init()
384 int cpu_eth_init(bd_t *bis)
386 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
387 tsec_standard_init(bis);