2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
33 /* ------------------------------------------------------------------------- */
38 uint lcrr; /* local bus clock ratio register */
39 uint clkdiv; /* clock divider portion of lcrr */
74 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
84 case PVR_FAM(PVR_85xx):
91 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
93 get_sys_info(&sysinfo);
95 puts("Clock Configuration:\n");
96 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
97 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
98 printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
100 #if defined(CFG_LBC_LCRR)
104 volatile immap_t *immap = (immap_t *)CFG_IMMR;
105 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
110 clkdiv = lcrr & 0x0f;
111 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
112 #ifdef CONFIG_MPC8548
114 * Yes, the entire PQ38 family use the same
115 * bit-representation for twice the clock divider values.
119 printf("LBC:%4lu MHz\n",
120 sysinfo.freqSystemBus / 1000000 / clkdiv);
122 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
125 if (ver == SVR_8560) {
126 printf("CPM: %lu Mhz\n",
127 sysinfo.freqSystemBus / 1000000);
130 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
136 /* ------------------------------------------------------------------------- */
138 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
141 * Initiate hard reset in debug control register DBCR0
142 * Make sure MSR[DE] = 1
155 * Get timebase clock frequency
157 unsigned long get_tbclk (void)
162 get_sys_info(&sys_info);
163 return ((sys_info.freqSystemBus + 7L) / 8L);
167 #if defined(CONFIG_WATCHDOG)
171 int re_enable = disable_interrupts();
172 reset_85xx_watchdog();
173 if (re_enable) enable_interrupts();
177 reset_85xx_watchdog(void)
180 * Clear TSR(WIS) bit by writing 1
187 #endif /* CONFIG_WATCHDOG */
189 #if defined(CONFIG_DDR_ECC)
190 void dma_init(void) {
191 volatile immap_t *immap = (immap_t *)CFG_IMMR;
192 volatile ccsr_dma_t *dma = &immap->im_dma;
194 dma->satr0 = 0x02c40000;
195 dma->datr0 = 0x02c40000;
196 asm("sync; isync; msync");
200 uint dma_check(void) {
201 volatile immap_t *immap = (immap_t *)CFG_IMMR;
202 volatile ccsr_dma_t *dma = &immap->im_dma;
203 volatile uint status = dma->sr0;
205 /* While the channel is busy, spin */
206 while((status & 4) == 4) {
211 printf ("DMA Error: status = %x\n", status);
216 int dma_xfer(void *dest, uint count, void *src) {
217 volatile immap_t *immap = (immap_t *)CFG_IMMR;
218 volatile ccsr_dma_t *dma = &immap->im_dma;
220 dma->dar0 = (uint) dest;
221 dma->sar0 = (uint) src;
223 dma->mr0 = 0xf000004;
224 asm("sync;isync;msync");
225 dma->mr0 = 0xf000005;
226 asm("sync;isync;msync");