2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <fsl_esdhc.h>
35 #include <asm/cache.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 struct cpu_type cpu_type_list [] = {
41 CPU_TYPE_ENTRY(8533, 8533),
42 CPU_TYPE_ENTRY(8533, 8533_E),
43 CPU_TYPE_ENTRY(8536, 8536),
44 CPU_TYPE_ENTRY(8536, 8536_E),
45 CPU_TYPE_ENTRY(8540, 8540),
46 CPU_TYPE_ENTRY(8541, 8541),
47 CPU_TYPE_ENTRY(8541, 8541_E),
48 CPU_TYPE_ENTRY(8543, 8543),
49 CPU_TYPE_ENTRY(8543, 8543_E),
50 CPU_TYPE_ENTRY(8544, 8544),
51 CPU_TYPE_ENTRY(8544, 8544_E),
52 CPU_TYPE_ENTRY(8545, 8545),
53 CPU_TYPE_ENTRY(8545, 8545_E),
54 CPU_TYPE_ENTRY(8547, 8547_E),
55 CPU_TYPE_ENTRY(8548, 8548),
56 CPU_TYPE_ENTRY(8548, 8548_E),
57 CPU_TYPE_ENTRY(8555, 8555),
58 CPU_TYPE_ENTRY(8555, 8555_E),
59 CPU_TYPE_ENTRY(8560, 8560),
60 CPU_TYPE_ENTRY(8567, 8567),
61 CPU_TYPE_ENTRY(8567, 8567_E),
62 CPU_TYPE_ENTRY(8568, 8568),
63 CPU_TYPE_ENTRY(8568, 8568_E),
64 CPU_TYPE_ENTRY(8569, 8569),
65 CPU_TYPE_ENTRY(8569, 8569_E),
66 CPU_TYPE_ENTRY(8572, 8572),
67 CPU_TYPE_ENTRY(8572, 8572_E),
68 CPU_TYPE_ENTRY(P2020, P2020),
69 CPU_TYPE_ENTRY(P2020, P2020_E),
72 struct cpu_type *identify_cpu(u32 ver)
75 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
76 if (cpu_type_list[i].soc_ver == ver)
77 return &cpu_type_list[i];
90 char buf1[32], buf2[32];
91 #ifdef CONFIG_DDR_CLK_FREQ
92 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
94 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
101 ver = SVR_SOC_VER(svr);
102 major = SVR_MAJ(svr);
103 #ifdef CONFIG_MPC8536
104 major &= 0x7; /* the msb of this nibble is a mfg code */
106 minor = SVR_MIN(svr);
108 #if (CONFIG_NUM_CPUS > 1)
109 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
110 printf("CPU%d: ", pic->whoami);
115 cpu = identify_cpu(ver);
119 if (IS_E_PROCESSOR(svr))
125 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
130 major = PVR_MAJ(pvr);
131 minor = PVR_MIN(pvr);
135 case PVR_FAM(PVR_85xx):
143 if (PVR_MEM(pvr) == 0x03)
146 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
148 get_sys_info(&sysinfo);
150 puts("Clock Configuration:");
151 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
154 printf("CPU%d:%-4s MHz, ",
155 i,strmhz(buf1, sysinfo.freqProcessor[i]));
157 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
161 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
162 strmhz(buf1, sysinfo.freqDDRBus/2),
163 strmhz(buf2, sysinfo.freqDDRBus));
166 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
167 strmhz(buf1, sysinfo.freqDDRBus/2),
168 strmhz(buf2, sysinfo.freqDDRBus));
171 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
172 strmhz(buf1, sysinfo.freqDDRBus/2),
173 strmhz(buf2, sysinfo.freqDDRBus));
177 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
178 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
180 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
181 sysinfo.freqLocalBus);
184 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
187 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
193 /* ------------------------------------------------------------------------- */
195 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
199 unsigned long val, msr;
205 /* e500 v2 core has reset control register */
206 volatile unsigned int * rstcr;
207 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
208 *rstcr = 0x2; /* HRESET_REQ */
213 * Fallthrough if the code above failed
214 * Initiate hard reset in debug control register DBCR0
215 * Make sure MSR[DE] = 1
231 * Get timebase clock frequency
233 unsigned long get_tbclk (void)
235 return (gd->bus_clk + 4UL)/8UL;
239 #if defined(CONFIG_WATCHDOG)
243 int re_enable = disable_interrupts();
244 reset_85xx_watchdog();
245 if (re_enable) enable_interrupts();
249 reset_85xx_watchdog(void)
252 * Clear TSR(WIS) bit by writing 1
255 val = mfspr(SPRN_TSR);
257 mtspr(SPRN_TSR, val);
259 #endif /* CONFIG_WATCHDOG */
261 #if defined(CONFIG_DDR_ECC)
262 void dma_init(void) {
263 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
265 dma->satr0 = 0x02c40000;
266 dma->datr0 = 0x02c40000;
267 dma->sr0 = 0xfffffff; /* clear any errors */
268 asm("sync; isync; msync");
272 uint dma_check(void) {
273 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
274 volatile uint status = dma->sr0;
276 /* While the channel is busy, spin */
277 while((status & 4) == 4) {
281 /* clear MR0[CS] channel start bit */
282 dma->mr0 &= 0x00000001;
283 asm("sync;isync;msync");
286 printf ("DMA Error: status = %x\n", status);
291 int dma_xfer(void *dest, uint count, void *src) {
292 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
294 dma->dar0 = (uint) dest;
295 dma->sar0 = (uint) src;
297 dma->mr0 = 0xf000004;
298 asm("sync;isync;msync");
299 dma->mr0 = 0xf000005;
300 asm("sync;isync;msync");
306 * Configures a UPM. The function requires the respective MxMR to be set
307 * before calling this function. "size" is the number or entries, not a sizeof.
309 void upmconfig (uint upm, uint * table, uint size)
311 int i, mdr, mad, old_mad = 0;
313 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
314 volatile u32 *brp,*orp;
315 volatile u8* dummy = NULL;
321 upmmask = BR_MS_UPMA;
325 upmmask = BR_MS_UPMB;
329 upmmask = BR_MS_UPMC;
332 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
336 /* Find the address for the dummy write transaction */
337 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
338 i++, brp += 2, orp += 2) {
340 /* Look for a valid BR with selected UPM */
341 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
342 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
348 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
352 for (i = 0; i < size; i++) {
354 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
356 out_be32(&lbc->mdr, table[i]);
358 mdr = in_be32(&lbc->mdr);
360 *(volatile u8 *)dummy = 0;
363 mad = in_be32(mxmr) & MxMR_MAD_MSK;
364 } while (mad <= old_mad && !(!mad && i == (size-1)));
367 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
372 * Initializes on-chip ethernet controllers.
373 * to override, implement board_eth_init()
375 int cpu_eth_init(bd_t *bis)
377 #if defined(CONFIG_ETHER_ON_FCC)
380 #if defined(CONFIG_UEC_ETH1)
383 #if defined(CONFIG_UEC_ETH2)
386 #if defined(CONFIG_UEC_ETH3)
389 #if defined(CONFIG_UEC_ETH4)
392 #if defined(CONFIG_UEC_ETH5)
395 #if defined(CONFIG_UEC_ETH6)
398 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
399 tsec_standard_init(bis);
406 * Initializes on-chip MMC controllers.
407 * to override, implement board_mmc_init()
409 int cpu_mmc_init(bd_t *bis)
411 #ifdef CONFIG_FSL_ESDHC
412 return fsl_esdhc_mmc_init(bis);