2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/cache.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type cpu_type_list [] = {
40 CPU_TYPE_ENTRY(8533, 8533),
41 CPU_TYPE_ENTRY(8533, 8533_E),
42 CPU_TYPE_ENTRY(8536, 8536),
43 CPU_TYPE_ENTRY(8536, 8536_E),
44 CPU_TYPE_ENTRY(8540, 8540),
45 CPU_TYPE_ENTRY(8541, 8541),
46 CPU_TYPE_ENTRY(8541, 8541_E),
47 CPU_TYPE_ENTRY(8543, 8543),
48 CPU_TYPE_ENTRY(8543, 8543_E),
49 CPU_TYPE_ENTRY(8544, 8544),
50 CPU_TYPE_ENTRY(8544, 8544_E),
51 CPU_TYPE_ENTRY(8545, 8545),
52 CPU_TYPE_ENTRY(8545, 8545_E),
53 CPU_TYPE_ENTRY(8547, 8547_E),
54 CPU_TYPE_ENTRY(8548, 8548),
55 CPU_TYPE_ENTRY(8548, 8548_E),
56 CPU_TYPE_ENTRY(8555, 8555),
57 CPU_TYPE_ENTRY(8555, 8555_E),
58 CPU_TYPE_ENTRY(8560, 8560),
59 CPU_TYPE_ENTRY(8567, 8567),
60 CPU_TYPE_ENTRY(8567, 8567_E),
61 CPU_TYPE_ENTRY(8568, 8568),
62 CPU_TYPE_ENTRY(8568, 8568_E),
63 CPU_TYPE_ENTRY(8572, 8572),
64 CPU_TYPE_ENTRY(8572, 8572_E),
67 struct cpu_type *identify_cpu(u32 ver)
70 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
71 if (cpu_type_list[i].soc_ver == ver)
72 return &cpu_type_list[i];
80 uint lcrr; /* local bus clock ratio register */
81 uint clkdiv; /* clock divider portion of lcrr */
87 char buf1[32], buf2[32];
88 #ifdef CONFIG_DDR_CLK_FREQ
89 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
91 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
97 ver = SVR_SOC_VER(svr);
100 major &= 0x7; /* the msb of this nibble is a mfg code */
102 minor = SVR_MIN(svr);
104 #if (CONFIG_NUM_CPUS > 1)
105 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
106 printf("CPU%d: ", pic->whoami);
111 cpu = identify_cpu(ver);
115 if (IS_E_PROCESSOR(svr))
121 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
126 major = PVR_MAJ(pvr);
127 minor = PVR_MIN(pvr);
131 case PVR_FAM(PVR_85xx):
139 if (PVR_MEM(pvr) == 0x03)
142 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
144 get_sys_info(&sysinfo);
146 puts("Clock Configuration:\n");
147 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
148 printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
152 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
153 strmhz(buf1, sysinfo.freqDDRBus/2),
154 strmhz(buf2, sysinfo.freqDDRBus));
157 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
158 strmhz(buf1, sysinfo.freqDDRBus/2),
159 strmhz(buf2, sysinfo.freqDDRBus));
162 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
163 strmhz(buf1, sysinfo.freqDDRBus/2),
164 strmhz(buf2, sysinfo.freqDDRBus));
168 #if defined(CONFIG_SYS_LBC_LCRR)
169 lcrr = CONFIG_SYS_LBC_LCRR;
172 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
177 clkdiv = lcrr & 0x0f;
178 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
179 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
180 defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
182 * Yes, the entire PQ38 family use the same
183 * bit-representation for twice the clock divider values.
187 printf("LBC:%-4s MHz\n",
188 strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
190 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
194 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
197 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
203 /* ------------------------------------------------------------------------- */
205 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
209 unsigned long val, msr;
215 /* e500 v2 core has reset control register */
216 volatile unsigned int * rstcr;
217 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
218 *rstcr = 0x2; /* HRESET_REQ */
223 * Fallthrough if the code above failed
224 * Initiate hard reset in debug control register DBCR0
225 * Make sure MSR[DE] = 1
241 * Get timebase clock frequency
243 unsigned long get_tbclk (void)
245 return (gd->bus_clk + 4UL)/8UL;
249 #if defined(CONFIG_WATCHDOG)
253 int re_enable = disable_interrupts();
254 reset_85xx_watchdog();
255 if (re_enable) enable_interrupts();
259 reset_85xx_watchdog(void)
262 * Clear TSR(WIS) bit by writing 1
265 val = mfspr(SPRN_TSR);
267 mtspr(SPRN_TSR, val);
269 #endif /* CONFIG_WATCHDOG */
271 #if defined(CONFIG_DDR_ECC)
272 void dma_init(void) {
273 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
275 dma->satr0 = 0x02c40000;
276 dma->datr0 = 0x02c40000;
277 dma->sr0 = 0xfffffff; /* clear any errors */
278 asm("sync; isync; msync");
282 uint dma_check(void) {
283 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
284 volatile uint status = dma->sr0;
286 /* While the channel is busy, spin */
287 while((status & 4) == 4) {
291 /* clear MR0[CS] channel start bit */
292 dma->mr0 &= 0x00000001;
293 asm("sync;isync;msync");
296 printf ("DMA Error: status = %x\n", status);
301 int dma_xfer(void *dest, uint count, void *src) {
302 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
304 dma->dar0 = (uint) dest;
305 dma->sar0 = (uint) src;
307 dma->mr0 = 0xf000004;
308 asm("sync;isync;msync");
309 dma->mr0 = 0xf000005;
310 asm("sync;isync;msync");
316 * Configures a UPM. The function requires the respective MxMR to be set
317 * before calling this function. "size" is the number or entries, not a sizeof.
319 void upmconfig (uint upm, uint * table, uint size)
321 int i, mdr, mad, old_mad = 0;
323 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
324 volatile u32 *brp,*orp;
325 volatile u8* dummy = NULL;
331 upmmask = BR_MS_UPMA;
335 upmmask = BR_MS_UPMB;
339 upmmask = BR_MS_UPMC;
342 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
346 /* Find the address for the dummy write transaction */
347 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
348 i++, brp += 2, orp += 2) {
350 /* Look for a valid BR with selected UPM */
351 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
352 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
358 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
362 for (i = 0; i < size; i++) {
364 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
366 out_be32(&lbc->mdr, table[i]);
368 mdr = in_be32(&lbc->mdr);
370 *(volatile u8 *)dummy = 0;
373 mad = in_be32(mxmr) & MxMR_MAD_MSK;
374 } while (mad <= old_mad && !(!mad && i == (size-1)));
377 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
382 * Initializes on-chip ethernet controllers.
383 * to override, implement board_eth_init()
385 int cpu_eth_init(bd_t *bis)
387 #if defined(CONFIG_ETHER_ON_FCC)
390 #if defined(CONFIG_UEC_ETH1)
393 #if defined(CONFIG_UEC_ETH2)
396 #if defined(CONFIG_UEC_ETH3)
399 #if defined(CONFIG_UEC_ETH4)
402 #if defined(CONFIG_UEC_ETH5)
405 #if defined(CONFIG_UEC_ETH6)
408 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
409 tsec_standard_init(bis);