2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <fsl_esdhc.h>
35 #include <asm/cache.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 struct cpu_type cpu_type_list [] = {
41 CPU_TYPE_ENTRY(8533, 8533),
42 CPU_TYPE_ENTRY(8533, 8533_E),
43 CPU_TYPE_ENTRY(8535, 8535),
44 CPU_TYPE_ENTRY(8535, 8535_E),
45 CPU_TYPE_ENTRY(8536, 8536),
46 CPU_TYPE_ENTRY(8536, 8536_E),
47 CPU_TYPE_ENTRY(8540, 8540),
48 CPU_TYPE_ENTRY(8541, 8541),
49 CPU_TYPE_ENTRY(8541, 8541_E),
50 CPU_TYPE_ENTRY(8543, 8543),
51 CPU_TYPE_ENTRY(8543, 8543_E),
52 CPU_TYPE_ENTRY(8544, 8544),
53 CPU_TYPE_ENTRY(8544, 8544_E),
54 CPU_TYPE_ENTRY(8545, 8545),
55 CPU_TYPE_ENTRY(8545, 8545_E),
56 CPU_TYPE_ENTRY(8547, 8547_E),
57 CPU_TYPE_ENTRY(8548, 8548),
58 CPU_TYPE_ENTRY(8548, 8548_E),
59 CPU_TYPE_ENTRY(8555, 8555),
60 CPU_TYPE_ENTRY(8555, 8555_E),
61 CPU_TYPE_ENTRY(8560, 8560),
62 CPU_TYPE_ENTRY(8567, 8567),
63 CPU_TYPE_ENTRY(8567, 8567_E),
64 CPU_TYPE_ENTRY(8568, 8568),
65 CPU_TYPE_ENTRY(8568, 8568_E),
66 CPU_TYPE_ENTRY(8569, 8569),
67 CPU_TYPE_ENTRY(8569, 8569_E),
68 CPU_TYPE_ENTRY(8572, 8572),
69 CPU_TYPE_ENTRY(8572, 8572_E),
70 CPU_TYPE_ENTRY(P2020, P2020),
71 CPU_TYPE_ENTRY(P2020, P2020_E),
74 struct cpu_type *identify_cpu(u32 ver)
77 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
78 if (cpu_type_list[i].soc_ver == ver)
79 return &cpu_type_list[i];
92 char buf1[32], buf2[32];
93 #ifdef CONFIG_DDR_CLK_FREQ
94 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
95 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
96 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
103 ver = SVR_SOC_VER(svr);
104 major = SVR_MAJ(svr);
105 #ifdef CONFIG_MPC8536
106 major &= 0x7; /* the msb of this nibble is a mfg code */
108 minor = SVR_MIN(svr);
110 #if (CONFIG_NUM_CPUS > 1)
111 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
112 printf("CPU%d: ", pic->whoami);
117 cpu = identify_cpu(ver);
121 if (IS_E_PROCESSOR(svr))
127 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
132 major = PVR_MAJ(pvr);
133 minor = PVR_MIN(pvr);
137 case PVR_FAM(PVR_85xx):
145 if (PVR_MEM(pvr) == 0x03)
148 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
150 get_sys_info(&sysinfo);
152 puts("Clock Configuration:");
153 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
156 printf("CPU%d:%-4s MHz, ",
157 i,strmhz(buf1, sysinfo.freqProcessor[i]));
159 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
163 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
164 strmhz(buf1, sysinfo.freqDDRBus/2),
165 strmhz(buf2, sysinfo.freqDDRBus));
168 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
169 strmhz(buf1, sysinfo.freqDDRBus/2),
170 strmhz(buf2, sysinfo.freqDDRBus));
173 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
174 strmhz(buf1, sysinfo.freqDDRBus/2),
175 strmhz(buf2, sysinfo.freqDDRBus));
179 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
180 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
182 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
183 sysinfo.freqLocalBus);
186 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
190 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
193 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
199 /* ------------------------------------------------------------------------- */
201 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
205 unsigned long val, msr;
211 /* e500 v2 core has reset control register */
212 volatile unsigned int * rstcr;
213 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
214 *rstcr = 0x2; /* HRESET_REQ */
219 * Fallthrough if the code above failed
220 * Initiate hard reset in debug control register DBCR0
221 * Make sure MSR[DE] = 1
237 * Get timebase clock frequency
239 unsigned long get_tbclk (void)
241 return (gd->bus_clk + 4UL)/8UL;
245 #if defined(CONFIG_WATCHDOG)
249 int re_enable = disable_interrupts();
250 reset_85xx_watchdog();
251 if (re_enable) enable_interrupts();
255 reset_85xx_watchdog(void)
258 * Clear TSR(WIS) bit by writing 1
261 val = mfspr(SPRN_TSR);
263 mtspr(SPRN_TSR, val);
265 #endif /* CONFIG_WATCHDOG */
267 #if defined(CONFIG_DDR_ECC)
268 void dma_init(void) {
269 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
271 dma->satr0 = 0x02c40000;
272 dma->datr0 = 0x02c40000;
273 dma->sr0 = 0xfffffff; /* clear any errors */
274 asm("sync; isync; msync");
278 uint dma_check(void) {
279 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
280 volatile uint status = dma->sr0;
282 /* While the channel is busy, spin */
283 while((status & 4) == 4) {
287 /* clear MR0[CS] channel start bit */
288 dma->mr0 &= 0x00000001;
289 asm("sync;isync;msync");
292 printf ("DMA Error: status = %x\n", status);
297 int dma_xfer(void *dest, uint count, void *src) {
298 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
300 dma->dar0 = (uint) dest;
301 dma->sar0 = (uint) src;
303 dma->mr0 = 0xf000004;
304 asm("sync;isync;msync");
305 dma->mr0 = 0xf000005;
306 asm("sync;isync;msync");
312 * Configures a UPM. The function requires the respective MxMR to be set
313 * before calling this function. "size" is the number or entries, not a sizeof.
315 void upmconfig (uint upm, uint * table, uint size)
317 int i, mdr, mad, old_mad = 0;
319 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
320 volatile u32 *brp,*orp;
321 volatile u8* dummy = NULL;
327 upmmask = BR_MS_UPMA;
331 upmmask = BR_MS_UPMB;
335 upmmask = BR_MS_UPMC;
338 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
342 /* Find the address for the dummy write transaction */
343 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
344 i++, brp += 2, orp += 2) {
346 /* Look for a valid BR with selected UPM */
347 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
348 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
354 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
358 for (i = 0; i < size; i++) {
360 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
362 out_be32(&lbc->mdr, table[i]);
364 mdr = in_be32(&lbc->mdr);
366 *(volatile u8 *)dummy = 0;
369 mad = in_be32(mxmr) & MxMR_MAD_MSK;
370 } while (mad <= old_mad && !(!mad && i == (size-1)));
373 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
378 * Initializes on-chip ethernet controllers.
379 * to override, implement board_eth_init()
381 int cpu_eth_init(bd_t *bis)
383 #if defined(CONFIG_ETHER_ON_FCC)
386 #if defined(CONFIG_UEC_ETH1)
389 #if defined(CONFIG_UEC_ETH2)
392 #if defined(CONFIG_UEC_ETH3)
395 #if defined(CONFIG_UEC_ETH4)
398 #if defined(CONFIG_UEC_ETH5)
401 #if defined(CONFIG_UEC_ETH6)
404 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
405 tsec_standard_init(bis);
412 * Initializes on-chip MMC controllers.
413 * to override, implement board_mmc_init()
415 int cpu_mmc_init(bd_t *bis)
417 #ifdef CONFIG_FSL_ESDHC
418 return fsl_esdhc_mmc_init(bis);