2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright 2004 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 * Set up GOT: Global Offset Table
63 * Use r14 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
76 GOT_ENTRY(__bss_start)
80 * Version string - must be in data segment because MPC83xx uses the
81 * first 256 bytes for the Hard Reset Configuration Word table (see
82 * below). Similarly, can't have the U-Boot Magic Number as the first
83 * thing in the image - don't know how this will affect the image tools,
84 * but I guess I'll find out soon.
90 .ascii " (", __DATE__, " - ", __TIME__, ")"
91 .ascii " ", CONFIG_IDENT_STRING, "\0"
94 #define _HRCW_TABLE_ENTRY(w) \
95 .fill 8,1,(((w)>>24)&0xff); \
96 .fill 8,1,(((w)>>16)&0xff); \
97 .fill 8,1,(((w)>> 8)&0xff); \
98 .fill 8,1,(((w) )&0xff)
100 _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
101 _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
105 #ifndef CONFIG_DEFAULT_IMMR
106 #error CONFIG_DEFAULT_IMMR must be defined
107 #endif /* CFG_DEFAULT_IMMR */
109 #define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
110 #endif /* CFG_IMMRBAR */
113 * After configuration, a system reset exception is executed using the
114 * vector at offset 0x100 relative to the base set by MSR[IP]. If
115 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
116 * base address is 0xfff00000. In the case of a Power On Reset or Hard
117 * Reset, the value of MSR[IP] is determined by the CIP field in the
120 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
121 * This determines the location of the boot ROM (flash or EPROM) in the
122 * processor's address space at boot time. As long as the HRCW is set up
123 * so that we eventually end up executing the code below when the
124 * processor executes the reset exception, the actual values used should
127 * Once we have got here, the address mask in OR0 is cleared so that the
128 * bottom 32K of the boot ROM is effectively repeated all throughout the
129 * processor's address space, after which we can jump to the absolute
130 * address at which the boot ROM was linked at compile time, and proceed
131 * to initialise the memory controller without worrying if the rug will
132 * be pulled out from under us, so to speak (it will be fine as long as
133 * we configure BR0 with the same boot ROM link address).
135 . = EXC_OFF_SYS_RESET
138 _start: /* time t 0 */
139 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
143 . = EXC_OFF_SYS_RESET + 0x10
147 li r21, BOOTFLAG_WARM /* Software reboot */
151 boot_cold: /* time t 3 */
152 lis r4, CONFIG_DEFAULT_IMMR@h
154 boot_warm: /* time t 5 */
155 mfmsr r5 /* save msr contents */
156 lis r3, CFG_IMMRBAR@h
157 ori r3, r3, CFG_IMMRBAR@l
160 /* Initialise the E300 processor core */
161 /*------------------------------------------*/
167 /* Inflate flash location so it appears everywhere, calculate */
168 /* the absolute address in final location of the FLASH, jump */
169 /* there and deflate the flash size back to minimal size */
170 /*------------------------------------------------------------*/
172 lis r4, (CFG_MONITOR_BASE)@h
173 ori r4, r4, (CFG_MONITOR_BASE)@l
174 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
178 #if 1 /* Remapping flash with LAW0. */
179 bl remap_flash_by_law0
181 #endif /* CFG_RAMBOOT */
183 bl setup_stack_in_data_cache_on_r1
185 /* let the C-code set up the rest */
187 /* Be careful to keep code relocatable & stack humble */
188 /*------------------------------------------------------*/
190 GET_GOT /* initialize GOT access */
193 lis r3, CFG_IMMRBAR@h
194 /* run low-level CPU init code (in Flash)*/
199 /* run 1st part of board init code (in Flash)*/
206 .globl _start_of_vectors
210 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
212 /* Data Storage exception. */
213 STD_EXCEPTION(0x300, DataStorage, UnknownException)
215 /* Instruction Storage exception. */
216 STD_EXCEPTION(0x400, InstStorage, UnknownException)
218 /* External Interrupt exception. */
220 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
223 /* Alignment exception. */
231 addi r3,r1,STACK_FRAME_OVERHEAD
233 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
234 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
235 lwz r6,GOT(transfer_to_handler)
239 .long AlignmentException - _start + EXC_OFF_SYS_RESET
240 .long int_return - _start + EXC_OFF_SYS_RESET
242 /* Program check exception */
246 addi r3,r1,STACK_FRAME_OVERHEAD
248 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
249 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
250 lwz r6,GOT(transfer_to_handler)
254 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
255 .long int_return - _start + EXC_OFF_SYS_RESET
257 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
259 /* I guess we could implement decrementer, and may have
260 * to someday for timekeeping.
262 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
264 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
265 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
266 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
267 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
269 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
270 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
272 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
273 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
274 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
278 * This exception occurs when the program counter matches the
279 * Instruction Address Breakpoint Register (IABR).
281 * I want the cpu to halt if this occurs so I can hunt around
282 * with the debugger and look at things.
284 * When DEBUG is defined, both machine check enable (in the MSR)
285 * and checkstop reset enable (in the reset mode register) are
286 * turned off and so a checkstop condition will result in the cpu
289 * I force the cpu into a checkstop condition by putting an illegal
290 * instruction here (at least this is the theory).
292 * well - that didnt work, so just do an infinite loop!
296 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
298 STD_EXCEPTION(0x1400, SMI, UnknownException)
300 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
301 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
302 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
303 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
304 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
305 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
306 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
307 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
308 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
309 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
310 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
311 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
312 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
313 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
314 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
315 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
316 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
317 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
318 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
319 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
320 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
321 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
322 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
323 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
324 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
325 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
326 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
329 .globl _end_of_vectors
335 * This code finishes saving the registers to the exception frame
336 * and jumps to the appropriate handler for the exception.
337 * Register r21 is pointer into trap frame, r1 has new stack pointer.
339 .globl transfer_to_handler
350 andi. r24,r23,0x3f00 /* get vector offset */
354 lwz r24,0(r23) /* virtual address of handler */
355 lwz r23,4(r23) /* where to go when done */
360 rfi /* jump to handler, enable MMU */
363 mfmsr r28 /* Disable interrupts */
367 SYNC /* Some chip revs need this... */
382 lwz r2,_NIP(r1) /* Restore environment */
393 * This code initialises the E300 processor core
394 * (conforms to PowerPC 603e spec)
395 * Note: expects original MSR contents to be in r5.
397 .globl init_e300_core
398 init_e300_core: /* time t 10 */
399 /* Initialize machine status; enable machine check interrupt */
400 /*-----------------------------------------------------------*/
402 li r3, MSR_KERNEL /* Set ME and RI flags */
403 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
405 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
407 SYNC /* Some chip revs need this... */
410 mtspr SRR1, r3 /* Make SRR1 match MSR */
413 lis r3, CFG_IMMRBAR@h
414 #if defined(CONFIG_WATCHDOG)
415 /* Initialise the Wathcdog values and reset it (if req) */
416 /*------------------------------------------------------*/
417 lis r4, CFG_WATCHDOG_VALUE
418 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
428 /* Disable Wathcdog */
429 /*-------------------*/
432 #endif /* CONFIG_WATCHDOG */
434 /* Initialize the Hardware Implementation-dependent Registers */
435 /* HID0 also contains cache control */
436 /*------------------------------------------------------*/
438 lis r3, CFG_HID0_INIT@h
439 ori r3, r3, CFG_HID0_INIT@l
443 lis r3, CFG_HID0_FINAL@h
444 ori r3, r3, CFG_HID0_FINAL@l
449 ori r3, r3, CFG_HID2@l
453 /* clear all BAT's */
454 /*----------------------------------*/
475 /* invalidate all tlb's
477 * From the 603e User Manual: "The 603e provides the ability to
478 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
479 * instruction invalidates the TLB entry indexed by the EA, and
480 * operates on both the instruction and data TLBs simultaneously
481 * invalidating four TLB entries (both sets in each TLB). The
482 * index corresponds to bits 15-19 of the EA. To invalidate all
483 * entries within both TLBs, 32 tlbie instructions should be
484 * issued, incrementing this field by one each time."
486 * "Note that the tlbia instruction is not implemented on the
489 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
490 * incrementing by 0x1000 each time. The code below is sort of
491 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
504 /*------------------------------*/
509 * Note: requires that all cache bits in
510 * HID0 are in the low half word.
517 ori r4, r4, HID0_ILOCK
519 ori r4, r3, HID0_ICFI
521 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
523 mtspr HID0, r3 /* clears invalidate */
526 .globl icache_disable
530 ori r4, r4, HID0_ICE|HID0_ILOCK
532 ori r4, r3, HID0_ICFI
534 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
536 mtspr HID0, r3 /* clears invalidate */
542 rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31
548 ori r3, r3, HID0_ENABLE_DATA_CACHE
550 ori r4, r4, HID0_LOCK_DATA_CACHE
552 ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE
554 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
556 mtspr HID0, r3 /* clears invalidate */
559 .globl dcache_disable
563 ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
565 ori r4, r3, HID0_INVALIDATE_DATA_CACHE
567 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
569 mtspr HID0, r3 /* clears invalidate */
575 rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31
583 /*-------------------------------------------------------------------*/
586 * void relocate_code (addr_sp, gd, addr_moni)
588 * This "function" does not return, instead it continues in RAM
589 * after relocating the monitor code.
593 * r5 = length in bytes
598 mr r1, r3 /* Set new stack pointer */
599 mr r9, r4 /* Save copy of Global Data pointer */
600 mr r10, r5 /* Save copy of Destination Address */
602 mr r3, r5 /* Destination Address */
603 lis r4, CFG_MONITOR_BASE@h /* Source Address */
604 ori r4, r4, CFG_MONITOR_BASE@l
605 lwz r5, GOT(__init_end)
607 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
612 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
613 * + Destination Address
619 /* First our own GOT */
621 /* then the one used by the C code */
631 beq cr1,4f /* In place copy is not necessary */
632 beq 7f /* Protect against 0 count */
661 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
671 * Now flush the cache: note that we must start from a cache aligned
672 * address. Otherwise we might miss one cache line.
675 bl un_setup_stack_in_data_cache
684 beq 7f /* Always flush prefetch queue in any case */
687 mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/
688 rlwinm r7,r7,HID0_DCE_SHIFT,31,31
696 sync /* Wait for all dcbst to complete on bus */
697 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
698 rlwinm r7,r7,HID0_DCE_SHIFT,31,31
706 7: sync /* Wait for all icbi to complete on bus */
710 * We are done. Do not return, instead branch to second part of board
711 * initialization, now running from RAM.
714 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
721 * Relocation Function, r14 point to got2+0x8000
723 * Adjust got2 pointers, no need to check for 0, this code
724 * already puts a few entries in the table.
726 li r0,__got2_entries@sectoff@l
727 la r3,GOT(_GOT2_TABLE_)
728 lwz r11,GOT(_GOT2_TABLE_)
738 * Now adjust the fixups and the pointers to the fixups
739 * in case we need to move ourselves again.
741 2: li r0,__fixup_entries@sectoff@l
742 lwz r3,GOT(_FIXUP_TABLE_)
756 * Now clear BSS segment
758 lwz r3,GOT(__bss_start)
759 #if defined(CONFIG_HYMOD)
761 * For HYMOD - the environment is the very last item in flash.
762 * The real .bss stops just before environment starts, so only
763 * clear up to that point.
765 * taken from mods for FADS board
767 lwz r4,GOT(environment)
783 mr r3, r9 /* Global Data pointer */
784 mr r4, r10 /* Destination Address */
788 * Copy exception vector code to low memory
791 * r7: source address, r8: end address, r9: target address
796 lwz r8, GOT(_end_of_vectors)
798 li r9, 0x100 /* reset vector always at 0x100 */
801 bgelr /* return if r7>=r8 - just in case */
803 mflr r4 /* save link register */
813 * relocate `hdlr' and `int_return' entries
815 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
816 li r8, Alignment - _start + EXC_OFF_SYS_RESET
819 addi r7, r7, 0x100 /* next exception vector */
823 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
826 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
829 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
830 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
833 addi r7, r7, 0x100 /* next exception vector */
837 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
838 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
841 addi r7, r7, 0x100 /* next exception vector */
845 mfmsr r3 /* now that the vectors have */
846 lis r7, MSR_IP@h /* relocated into low memory */
847 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
848 andc r3, r3, r7 /* (if it was on) */
849 SYNC /* Some chip revs need this... */
853 mtlr r4 /* restore link register */
857 * Function: relocate entries for one exception vector
860 lwz r0, 0(r7) /* hdlr ... */
861 add r0, r0, r3 /* ... += dest_addr */
864 lwz r0, 4(r7) /* int_return ... */
865 add r0, r0, r3 /* ... += dest_addr */
870 #ifdef CFG_INIT_RAM_LOCK
871 .globl unlock_ram_in_cache
873 /* invalidate the INIT_RAM section */
874 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
875 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
882 sync /* Wait for all icbi to complete on bus */
888 /* When booting from ROM (Flash or EPROM), clear the */
889 /* Address Mask in OR0 so ROM appears everywhere */
890 /*----------------------------------------------------*/
891 lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */
893 li r5, 0x7fff /* r5 <= 0x00007FFFF */
895 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
897 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
898 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
899 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
900 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
901 * 0xFF800. From the hard resetting to here, the processor fetched and
902 * executed the instructions one by one. There is not absolutely
903 * jumping happened. Laterly, the u-boot code has to do an absolutely
904 * jumping to tell the CPU instruction fetching component what the
905 * u-boot TEXT base address is. Because the TEXT base resides in the
906 * boot ROM memory space, to garantee the code can run smoothly after
907 * that jumping, we must map in the entire boot ROM by Local Access
908 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
909 * address for boot ROM, such as 0xFE000000. In this case, the default
910 * LBIU Local Access Widow 0 will not cover this memory space. So, we
911 * need another window to map in it.
913 lis r4, (CFG_FLASH_BASE)@h
914 ori r4, r4, (CFG_FLASH_BASE)@l
915 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
916 lis r4, (0x80000016)@h
917 ori r4, r4, (0x80000016)@l
918 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
921 /* Though all the LBIU Local Access Windows and LBC Banks will be
922 * initialized in the C code, we'd better configure boot ROM's
923 * window 0 and bank 0 correctly at here.
926 /* Initialize the BR0 with the boot ROM starting address. */
930 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
931 ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
933 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
936 lis r5, 0xFF80 /* 8M */
938 stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */
940 lis r4, (CFG_FLASH_BASE)@h
941 ori r4, r4, (CFG_FLASH_BASE)@l
942 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
944 lis r4, (0x80000016)@h
945 ori r4, r4, (0x80000016)@l
946 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */
949 stw r4, LBLAWBAR1(r3)
950 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
953 setup_stack_in_data_cache_on_r1:
954 lis r3, (CFG_IMMRBAR)@h
956 /* setup D-BAT for the D-Cache (with out real memory backup) */
958 lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
967 ori r4, r4, (MSR_DR | MSR_IR)@l
971 /* Enable and invalidate data cache. */
974 ori r4, r4, HID0_DCE | HID0_DCI
981 /* Allocate Initial RAM in data cache.*/
983 lis r4, (CFG_INIT_RAM_ADDR)@h
984 ori r4, r4, (CFG_INIT_RAM_ADDR)@l
985 li r5, 128*8 /* 128*8*32=32Kb */
993 /* Lock all the D-cache, basically leaving the reset of the program without dcache */
995 ori r4, r4, (HID0_DLOCK)@l
999 /* setup the stack pointer in r1 */
1000 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
1001 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
1002 li r0, 0 /* Make room for stack frame header and */
1004 stwu r0, -4(r1) /* clear final stack frame so that */
1005 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1009 un_setup_stack_in_data_cache:
1015 lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
1021 /* un lock all the D-cache */
1023 lis r5, (~(HID0_DLOCK))@h
1024 ori r5, r5, (~(HID0_DLOCK))@l
1029 /* Re - Allocate Initial RAM in data cache.*/
1031 lis r4, (CFG_INIT_RAM_ADDR)@h
1032 ori r4, r4, (CFG_INIT_RAM_ADDR)@l
1033 li r5, 128*8 /* 128*8*32=32Kb */
1048 #define GREEN_LIGHT 0x2B0D4046
1049 #define RED_LIGHT 0x250D4046
1050 #define LIB_CNT 0x4FFF
1058 lis r3, CFG_IMMRBAR@h
1059 ori r3, r3, CFG_IMMRBAR@l
1065 lis r4, 0xF8000000@h
1066 ori r4, r4, 0xF8000000@l
1067 stw r4, LBLAWBAR1(r3)
1068 lis r4, 0x8000000E@h
1069 ori r4, r4, 0x8000000E@l
1070 stw r4, LBLAWAR1(r3)
1071 lis r4, 0xF8000801@h
1072 ori r4, r4, 0xF8000801@l
1074 lis r4, 0xFFFFE8f0@h
1075 ori r4, r4, 0xFFFFE8f0@l
1078 lis r4, 0xF8000000@h
1079 ori r4, r4, 0xF8000000@l
1080 lis r5, GREEN_LIGHT@h
1081 ori r5, r5, GREEN_LIGHT@l
1083 ori r6, r6, RED_LIGHT@l
1085 ori r7, r7, LIB_CNT@l