2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright 2004 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 * Set up GOT: Global Offset Table
63 * Use r14 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
76 GOT_ENTRY(__bss_start)
80 * Version string - must be in data segment because MPC83xx uses the
81 * first 256 bytes for the Hard Reset Configuration Word table (see
82 * below). Similarly, can't have the U-Boot Magic Number as the first
83 * thing in the image - don't know how this will affect the image tools,
84 * but I guess I'll find out soon.
90 .ascii " (", __DATE__, " - ", __TIME__, ")"
91 .ascii " ", CONFIG_IDENT_STRING, "\0"
94 #define _HRCW_TABLE_ENTRY(w) \
95 .fill 8,1,(((w)>>24)&0xff); \
96 .fill 8,1,(((w)>>16)&0xff); \
97 .fill 8,1,(((w)>> 8)&0xff); \
98 .fill 8,1,(((w) )&0xff)
100 _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
101 _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
104 #ifndef CONFIG_DEFAULT_IMMR
105 #error CONFIG_DEFAULT_IMMR must be defined
106 #endif /* CFG_DEFAULT_IMMR */
108 #define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
109 #endif /* CFG_IMMRBAR */
112 * After configuration, a system reset exception is executed using the
113 * vector at offset 0x100 relative to the base set by MSR[IP]. If
114 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
115 * base address is 0xfff00000. In the case of a Power On Reset or Hard
116 * Reset, the value of MSR[IP] is determined by the CIP field in the
119 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
120 * This determines the location of the boot ROM (flash or EPROM) in the
121 * processor's address space at boot time. As long as the HRCW is set up
122 * so that we eventually end up executing the code below when the
123 * processor executes the reset exception, the actual values used should
126 * Once we have got here, the address mask in OR0 is cleared so that the
127 * bottom 32K of the boot ROM is effectively repeated all throughout the
128 * processor's address space, after which we can jump to the absolute
129 * address at which the boot ROM was linked at compile time, and proceed
130 * to initialise the memory controller without worrying if the rug will
131 * be pulled out from under us, so to speak (it will be fine as long as
132 * we configure BR0 with the same boot ROM link address).
134 . = EXC_OFF_SYS_RESET
137 _start: /* time t 0 */
138 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
142 . = EXC_OFF_SYS_RESET + 0x10
146 li r21, BOOTFLAG_WARM /* Software reboot */
150 boot_cold: /* time t 3 */
151 lis r4, CONFIG_DEFAULT_IMMR@h
153 boot_warm: /* time t 5 */
154 mfmsr r5 /* save msr contents */
155 lis r3, CFG_IMMRBAR@h
156 ori r3, r3, CFG_IMMRBAR@l
159 /* Initialise the E300 processor core */
160 /*------------------------------------------*/
166 /* Inflate flash location so it appears everywhere, calculate */
167 /* the absolute address in final location of the FLASH, jump */
168 /* there and deflate the flash size back to minimal size */
169 /*------------------------------------------------------------*/
171 lis r4, (CFG_MONITOR_BASE)@h
172 ori r4, r4, (CFG_MONITOR_BASE)@l
173 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
177 #if 1 /* Remapping flash with LAW0. */
178 bl remap_flash_by_law0
180 #endif /* CFG_RAMBOOT */
182 bl setup_stack_in_data_cache_on_r1
184 /* let the C-code set up the rest */
186 /* Be careful to keep code relocatable & stack humble */
187 /*------------------------------------------------------*/
189 GET_GOT /* initialize GOT access */
192 lis r3, CFG_IMMRBAR@h
193 /* run low-level CPU init code (in Flash)*/
198 /* run 1st part of board init code (in Flash)*/
205 .globl _start_of_vectors
209 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
211 /* Data Storage exception. */
212 STD_EXCEPTION(0x300, DataStorage, UnknownException)
214 /* Instruction Storage exception. */
215 STD_EXCEPTION(0x400, InstStorage, UnknownException)
217 /* External Interrupt exception. */
219 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
222 /* Alignment exception. */
230 addi r3,r1,STACK_FRAME_OVERHEAD
232 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
233 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
234 lwz r6,GOT(transfer_to_handler)
238 .long AlignmentException - _start + EXC_OFF_SYS_RESET
239 .long int_return - _start + EXC_OFF_SYS_RESET
241 /* Program check exception */
245 addi r3,r1,STACK_FRAME_OVERHEAD
247 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
248 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
249 lwz r6,GOT(transfer_to_handler)
253 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
254 .long int_return - _start + EXC_OFF_SYS_RESET
256 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
258 /* I guess we could implement decrementer, and may have
259 * to someday for timekeeping.
261 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
263 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
264 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
265 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
266 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
268 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
269 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
271 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
272 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
273 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
277 * This exception occurs when the program counter matches the
278 * Instruction Address Breakpoint Register (IABR).
280 * I want the cpu to halt if this occurs so I can hunt around
281 * with the debugger and look at things.
283 * When DEBUG is defined, both machine check enable (in the MSR)
284 * and checkstop reset enable (in the reset mode register) are
285 * turned off and so a checkstop condition will result in the cpu
288 * I force the cpu into a checkstop condition by putting an illegal
289 * instruction here (at least this is the theory).
291 * well - that didnt work, so just do an infinite loop!
295 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
297 STD_EXCEPTION(0x1400, SMI, UnknownException)
299 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
300 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
301 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
302 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
303 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
304 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
305 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
306 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
307 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
308 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
309 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
310 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
311 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
312 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
313 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
314 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
315 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
316 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
317 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
318 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
319 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
320 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
321 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
322 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
323 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
324 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
325 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
328 .globl _end_of_vectors
334 * This code finishes saving the registers to the exception frame
335 * and jumps to the appropriate handler for the exception.
336 * Register r21 is pointer into trap frame, r1 has new stack pointer.
338 .globl transfer_to_handler
349 andi. r24,r23,0x3f00 /* get vector offset */
353 lwz r24,0(r23) /* virtual address of handler */
354 lwz r23,4(r23) /* where to go when done */
359 rfi /* jump to handler, enable MMU */
362 mfmsr r28 /* Disable interrupts */
366 SYNC /* Some chip revs need this... */
381 lwz r2,_NIP(r1) /* Restore environment */
392 * This code initialises the E300 processor core
393 * (conforms to PowerPC 603e spec)
394 * Note: expects original MSR contents to be in r5.
396 .globl init_e300_core
397 init_e300_core: /* time t 10 */
398 /* Initialize machine status; enable machine check interrupt */
399 /*-----------------------------------------------------------*/
401 li r3, MSR_KERNEL /* Set ME and RI flags */
402 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
404 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
406 SYNC /* Some chip revs need this... */
409 mtspr SRR1, r3 /* Make SRR1 match MSR */
412 lis r3, CFG_IMMRBAR@h
413 #if defined(CONFIG_WATCHDOG)
414 /* Initialise the Wathcdog values and reset it (if req) */
415 /*------------------------------------------------------*/
416 lis r4, CFG_WATCHDOG_VALUE
417 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
427 /* Disable Wathcdog */
428 /*-------------------*/
431 #endif /* CONFIG_WATCHDOG */
433 /* Initialize the Hardware Implementation-dependent Registers */
434 /* HID0 also contains cache control */
435 /*------------------------------------------------------*/
437 lis r3, CFG_HID0_INIT@h
438 ori r3, r3, CFG_HID0_INIT@l
442 lis r3, CFG_HID0_FINAL@h
443 ori r3, r3, CFG_HID0_FINAL@l
448 ori r3, r3, CFG_HID2@l
452 /* clear all BAT's */
453 /*----------------------------------*/
474 /* invalidate all tlb's
476 * From the 603e User Manual: "The 603e provides the ability to
477 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
478 * instruction invalidates the TLB entry indexed by the EA, and
479 * operates on both the instruction and data TLBs simultaneously
480 * invalidating four TLB entries (both sets in each TLB). The
481 * index corresponds to bits 15-19 of the EA. To invalidate all
482 * entries within both TLBs, 32 tlbie instructions should be
483 * issued, incrementing this field by one each time."
485 * "Note that the tlbia instruction is not implemented on the
488 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
489 * incrementing by 0x1000 each time. The code below is sort of
490 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
503 /*------------------------------*/
508 * Note: requires that all cache bits in
509 * HID0 are in the low half word.
516 ori r4, r4, HID0_ILOCK
518 ori r4, r3, HID0_ICFI
520 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
522 mtspr HID0, r3 /* clears invalidate */
525 .globl icache_disable
529 ori r4, r4, HID0_ICE|HID0_ILOCK
531 ori r4, r3, HID0_ICFI
533 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
535 mtspr HID0, r3 /* clears invalidate */
541 rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31
547 ori r3, r3, HID0_ENABLE_DATA_CACHE
549 ori r4, r4, HID0_LOCK_DATA_CACHE
551 ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE
553 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
555 mtspr HID0, r3 /* clears invalidate */
558 .globl dcache_disable
562 ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
564 ori r4, r3, HID0_INVALIDATE_DATA_CACHE
566 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
568 mtspr HID0, r3 /* clears invalidate */
574 rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31
582 /*-------------------------------------------------------------------*/
585 * void relocate_code (addr_sp, gd, addr_moni)
587 * This "function" does not return, instead it continues in RAM
588 * after relocating the monitor code.
592 * r5 = length in bytes
597 mr r1, r3 /* Set new stack pointer */
598 mr r9, r4 /* Save copy of Global Data pointer */
599 mr r10, r5 /* Save copy of Destination Address */
601 mr r3, r5 /* Destination Address */
602 lis r4, CFG_MONITOR_BASE@h /* Source Address */
603 ori r4, r4, CFG_MONITOR_BASE@l
604 lwz r5, GOT(__init_end)
606 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
611 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
612 * + Destination Address
618 /* First our own GOT */
620 /* then the one used by the C code */
630 beq cr1,4f /* In place copy is not necessary */
631 beq 7f /* Protect against 0 count */
660 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
668 * Now flush the cache: note that we must start from a cache aligned
669 * address. Otherwise we might miss one cache line.
672 bl un_setup_stack_in_data_cache
681 beq 7f /* Always flush prefetch queue in any case */
684 mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/
685 rlwinm r7,r7,HID0_DCE_SHIFT,31,31
693 sync /* Wait for all dcbst to complete on bus */
694 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
695 rlwinm r7,r7,HID0_DCE_SHIFT,31,31
703 7: sync /* Wait for all icbi to complete on bus */
707 * We are done. Do not return, instead branch to second part of board
708 * initialization, now running from RAM.
711 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
718 * Relocation Function, r14 point to got2+0x8000
720 * Adjust got2 pointers, no need to check for 0, this code
721 * already puts a few entries in the table.
723 li r0,__got2_entries@sectoff@l
724 la r3,GOT(_GOT2_TABLE_)
725 lwz r11,GOT(_GOT2_TABLE_)
735 * Now adjust the fixups and the pointers to the fixups
736 * in case we need to move ourselves again.
738 2: li r0,__fixup_entries@sectoff@l
739 lwz r3,GOT(_FIXUP_TABLE_)
753 * Now clear BSS segment
755 lwz r3,GOT(__bss_start)
756 #if defined(CONFIG_HYMOD)
758 * For HYMOD - the environment is the very last item in flash.
759 * The real .bss stops just before environment starts, so only
760 * clear up to that point.
762 * taken from mods for FADS board
764 lwz r4,GOT(environment)
780 mr r3, r9 /* Global Data pointer */
781 mr r4, r10 /* Destination Address */
785 * Copy exception vector code to low memory
788 * r7: source address, r8: end address, r9: target address
793 lwz r8, GOT(_end_of_vectors)
795 li r9, 0x100 /* reset vector always at 0x100 */
798 bgelr /* return if r7>=r8 - just in case */
800 mflr r4 /* save link register */
810 * relocate `hdlr' and `int_return' entries
812 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
813 li r8, Alignment - _start + EXC_OFF_SYS_RESET
816 addi r7, r7, 0x100 /* next exception vector */
820 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
823 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
826 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
827 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
830 addi r7, r7, 0x100 /* next exception vector */
834 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
835 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
838 addi r7, r7, 0x100 /* next exception vector */
842 mfmsr r3 /* now that the vectors have */
843 lis r7, MSR_IP@h /* relocated into low memory */
844 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
845 andc r3, r3, r7 /* (if it was on) */
846 SYNC /* Some chip revs need this... */
850 mtlr r4 /* restore link register */
854 * Function: relocate entries for one exception vector
857 lwz r0, 0(r7) /* hdlr ... */
858 add r0, r0, r3 /* ... += dest_addr */
861 lwz r0, 4(r7) /* int_return ... */
862 add r0, r0, r3 /* ... += dest_addr */
867 #ifdef CFG_INIT_RAM_LOCK
868 .globl unlock_ram_in_cache
870 /* invalidate the INIT_RAM section */
871 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
872 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
879 sync /* Wait for all icbi to complete on bus */
885 /* When booting from ROM (Flash or EPROM), clear the */
886 /* Address Mask in OR0 so ROM appears everywhere */
887 /*----------------------------------------------------*/
888 lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */
890 li r5, 0x7fff /* r5 <= 0x00007FFFF */
892 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
894 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
895 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
896 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
897 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
898 * 0xFF800. From the hard resetting to here, the processor fetched and
899 * executed the instructions one by one. There is not absolutely
900 * jumping happened. Laterly, the u-boot code has to do an absolutely
901 * jumping to tell the CPU instruction fetching component what the
902 * u-boot TEXT base address is. Because the TEXT base resides in the
903 * boot ROM memory space, to garantee the code can run smoothly after
904 * that jumping, we must map in the entire boot ROM by Local Access
905 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
906 * address for boot ROM, such as 0xFE000000. In this case, the default
907 * LBIU Local Access Widow 0 will not cover this memory space. So, we
908 * need another window to map in it.
910 lis r4, (CFG_FLASH_BASE)@h
911 ori r4, r4, (CFG_FLASH_BASE)@l
912 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
913 lis r4, (0x80000016)@h
914 ori r4, r4, (0x80000016)@l
915 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
918 /* Though all the LBIU Local Access Windows and LBC Banks will be
919 * initialized in the C code, we'd better configure boot ROM's
920 * window 0 and bank 0 correctly at here.
923 /* Initialize the BR0 with the boot ROM starting address. */
927 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
928 ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
930 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
933 lis r5, 0xFF80 /* 8M */
935 stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */
937 lis r4, (CFG_FLASH_BASE)@h
938 ori r4, r4, (CFG_FLASH_BASE)@l
939 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
941 lis r4, (0x80000016)@h
942 ori r4, r4, (0x80000016)@l
943 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */
946 stw r4, LBLAWBAR1(r3)
947 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
950 setup_stack_in_data_cache_on_r1:
951 lis r3, (CFG_IMMRBAR)@h
953 /* setup D-BAT for the D-Cache (with out real memory backup) */
955 lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
964 ori r4, r4, (MSR_DR | MSR_IR)@l
968 /* Enable and invalidate data cache. */
971 ori r4, r4, HID0_DCE | HID0_DCI
978 /* Allocate Initial RAM in data cache.*/
980 lis r4, (CFG_INIT_RAM_ADDR)@h
981 ori r4, r4, (CFG_INIT_RAM_ADDR)@l
982 li r5, 128*8 /* 128*8*32=32Kb */
990 /* Lock all the D-cache, basically leaving the reset of the program without dcache */
992 ori r4, r4, (HID0_DLOCK)@l
996 /* setup the stack pointer in r1 */
997 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
998 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
999 li r0, 0 /* Make room for stack frame header and */
1001 stwu r0, -4(r1) /* clear final stack frame so that */
1002 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1006 un_setup_stack_in_data_cache:
1012 lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
1018 /* un lock all the D-cache */
1020 lis r5, (~(HID0_DLOCK))@h
1021 ori r5, r5, (~(HID0_DLOCK))@l
1026 /* Re - Allocate Initial RAM in data cache.*/
1028 lis r4, (CFG_INIT_RAM_ADDR)@h
1029 ori r4, r4, (CFG_INIT_RAM_ADDR)@l
1030 li r5, 128*8 /* 128*8*32=32Kb */
1045 #define GREEN_LIGHT 0x2B0D4046
1046 #define RED_LIGHT 0x250D4046
1047 #define LIB_CNT 0x4FFF
1055 lis r3, CFG_IMMRBAR@h
1056 ori r3, r3, CFG_IMMRBAR@l
1062 lis r4, 0xF8000000@h
1063 ori r4, r4, 0xF8000000@l
1064 stw r4, LBLAWBAR1(r3)
1065 lis r4, 0x8000000E@h
1066 ori r4, r4, 0x8000000E@l
1067 stw r4, LBLAWAR1(r3)
1068 lis r4, 0xF8000801@h
1069 ori r4, r4, 0xF8000801@l
1071 lis r4, 0xFFFFE8f0@h
1072 ori r4, r4, 0xFFFFE8f0@l
1075 lis r4, 0xF8000000@h
1076 ori r4, r4, 0xF8000000@l
1077 lis r5, GREEN_LIGHT@h
1078 ori r5, r5, GREEN_LIGHT@l
1080 ori r6, r6, RED_LIGHT@l
1082 ori r7, r7, LIB_CNT@l