2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
32 #include <timestamp.h>
35 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING "MPC83XX"
48 /* We don't want the MMU yet.
53 * Floating Point enable, Machine Check and Recoverable Interr.
56 #define MSR_KERNEL (MSR_FP|MSR_RI)
58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
62 #define CONFIG_SYS_FLASHBOOT
66 * Set up GOT: Global Offset Table
68 * Use r14 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(__bss_start)
75 #ifndef CONFIG_NAND_SPL
76 GOT_ENTRY(_FIXUP_TABLE_)
78 GOT_ENTRY(_start_of_vectors)
79 GOT_ENTRY(_end_of_vectors)
80 GOT_ENTRY(transfer_to_handler)
85 * The Hard Reset Configuration Word (HRCW) table is in the first 64
86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
87 * times so the processor can fetch it out of flash whether the flash
88 * is 8, 16, 32, or 64 bits wide (hardware trickery).
91 #define _HRCW_TABLE_ENTRY(w) \
92 .fill 8,1,(((w)>>24)&0xff); \
93 .fill 8,1,(((w)>>16)&0xff); \
94 .fill 8,1,(((w)>> 8)&0xff); \
95 .fill 8,1,(((w) )&0xff)
97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
101 * Magic number and version string - put it after the HRCW since it
102 * cannot be first in flash like it is in many other processors.
104 .long 0x27051956 /* U-Boot Magic Number */
106 .globl version_string
108 .ascii U_BOOT_VERSION
109 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
110 .ascii " ", CONFIG_IDENT_STRING, "\0"
113 #ifndef CONFIG_DEFAULT_IMMR
114 #error CONFIG_DEFAULT_IMMR must be defined
115 #endif /* CONFIG_SYS_DEFAULT_IMMR */
116 #ifndef CONFIG_SYS_IMMR
117 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
118 #endif /* CONFIG_SYS_IMMR */
121 * After configuration, a system reset exception is executed using the
122 * vector at offset 0x100 relative to the base set by MSR[IP]. If
123 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
124 * base address is 0xfff00000. In the case of a Power On Reset or Hard
125 * Reset, the value of MSR[IP] is determined by the CIP field in the
128 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
129 * This determines the location of the boot ROM (flash or EPROM) in the
130 * processor's address space at boot time. As long as the HRCW is set up
131 * so that we eventually end up executing the code below when the
132 * processor executes the reset exception, the actual values used should
135 * Once we have got here, the address mask in OR0 is cleared so that the
136 * bottom 32K of the boot ROM is effectively repeated all throughout the
137 * processor's address space, after which we can jump to the absolute
138 * address at which the boot ROM was linked at compile time, and proceed
139 * to initialise the memory controller without worrying if the rug will
140 * be pulled out from under us, so to speak (it will be fine as long as
141 * we configure BR0 with the same boot ROM link address).
143 . = EXC_OFF_SYS_RESET
146 _start: /* time t 0 */
147 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
151 . = EXC_OFF_SYS_RESET + 0x10
155 li r21, BOOTFLAG_WARM /* Software reboot */
159 boot_cold: /* time t 3 */
160 lis r4, CONFIG_DEFAULT_IMMR@h
162 boot_warm: /* time t 5 */
163 mfmsr r5 /* save msr contents */
164 lis r3, CONFIG_SYS_IMMR@h
165 ori r3, r3, CONFIG_SYS_IMMR@l
168 /* Initialise the E300 processor core */
169 /*------------------------------------------*/
171 #ifdef CONFIG_NAND_SPL
172 /* The FCM begins execution after only the first page
173 * is loaded. Wait for the rest before branching
174 * to another flash page.
185 #ifdef CONFIG_SYS_FLASHBOOT
187 /* Inflate flash location so it appears everywhere, calculate */
188 /* the absolute address in final location of the FLASH, jump */
189 /* there and deflate the flash size back to minimal size */
190 /*------------------------------------------------------------*/
192 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
193 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
194 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
198 #if 1 /* Remapping flash with LAW0. */
199 bl remap_flash_by_law0
201 #endif /* CONFIG_SYS_FLASHBOOT */
208 * Cache must be enabled here for stack-in-cache trick.
209 * This means we need to enable the BATS.
211 * 1) for the EVB, original gt regs need to be mapped
212 * 2) need to have an IBAT for the 0xf region,
213 * we are running there!
214 * Cache should be turned on after BATs, since by default
215 * everything is write-through.
216 * The init-mem BAT can be reused after reloc. The old
217 * gt-regs BAT can be reused after board_init_f calls
218 * board_early_init_f (EVB only).
220 /* enable address translation */
224 /* enable the data cache */
227 #ifdef CONFIG_SYS_INIT_RAM_LOCK
232 /* set up the stack pointer in our newly created
234 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
235 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
237 li r0, 0 /* Make room for stack frame header and */
238 stwu r0, -4(r1) /* clear final stack frame so that */
239 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
242 /* let the C-code set up the rest */
244 /* Be careful to keep code relocatable & stack humble */
245 /*------------------------------------------------------*/
247 GET_GOT /* initialize GOT access */
250 lis r3, CONFIG_SYS_IMMR@h
251 /* run low-level CPU init code (in Flash)*/
256 /* run 1st part of board init code (in Flash)*/
259 #ifndef CONFIG_NAND_SPL
264 .globl _start_of_vectors
268 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
270 /* Data Storage exception. */
271 STD_EXCEPTION(0x300, DataStorage, UnknownException)
273 /* Instruction Storage exception. */
274 STD_EXCEPTION(0x400, InstStorage, UnknownException)
276 /* External Interrupt exception. */
278 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
281 /* Alignment exception. */
284 EXCEPTION_PROLOG(SRR0, SRR1)
289 addi r3,r1,STACK_FRAME_OVERHEAD
291 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
292 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
293 lwz r6,GOT(transfer_to_handler)
297 .long AlignmentException - _start + EXC_OFF_SYS_RESET
298 .long int_return - _start + EXC_OFF_SYS_RESET
300 /* Program check exception */
303 EXCEPTION_PROLOG(SRR0, SRR1)
304 addi r3,r1,STACK_FRAME_OVERHEAD
306 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
307 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
308 lwz r6,GOT(transfer_to_handler)
312 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
313 .long int_return - _start + EXC_OFF_SYS_RESET
315 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
317 /* I guess we could implement decrementer, and may have
318 * to someday for timekeeping.
320 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
322 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
323 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
324 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
325 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
327 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
328 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
330 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
331 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
332 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
336 * This exception occurs when the program counter matches the
337 * Instruction Address Breakpoint Register (IABR).
339 * I want the cpu to halt if this occurs so I can hunt around
340 * with the debugger and look at things.
342 * When DEBUG is defined, both machine check enable (in the MSR)
343 * and checkstop reset enable (in the reset mode register) are
344 * turned off and so a checkstop condition will result in the cpu
347 * I force the cpu into a checkstop condition by putting an illegal
348 * instruction here (at least this is the theory).
350 * well - that didnt work, so just do an infinite loop!
354 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
356 STD_EXCEPTION(0x1400, SMI, UnknownException)
358 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
359 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
360 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
361 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
362 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
363 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
364 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
365 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
366 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
367 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
368 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
369 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
370 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
371 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
372 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
373 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
374 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
375 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
376 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
377 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
378 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
379 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
380 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
381 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
382 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
383 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
384 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
387 .globl _end_of_vectors
393 * This code finishes saving the registers to the exception frame
394 * and jumps to the appropriate handler for the exception.
395 * Register r21 is pointer into trap frame, r1 has new stack pointer.
397 .globl transfer_to_handler
408 andi. r24,r23,0x3f00 /* get vector offset */
412 lwz r24,0(r23) /* virtual address of handler */
413 lwz r23,4(r23) /* where to go when done */
418 rfi /* jump to handler, enable MMU */
421 mfmsr r28 /* Disable interrupts */
425 SYNC /* Some chip revs need this... */
440 lwz r2,_NIP(r1) /* Restore environment */
449 #endif /* !CONFIG_NAND_SPL */
452 * This code initialises the E300 processor core
453 * (conforms to PowerPC 603e spec)
454 * Note: expects original MSR contents to be in r5.
456 .globl init_e300_core
457 init_e300_core: /* time t 10 */
458 /* Initialize machine status; enable machine check interrupt */
459 /*-----------------------------------------------------------*/
461 li r3, MSR_KERNEL /* Set ME and RI flags */
462 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
464 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
466 SYNC /* Some chip revs need this... */
469 mtspr SRR1, r3 /* Make SRR1 match MSR */
472 lis r3, CONFIG_SYS_IMMR@h
473 #if defined(CONFIG_WATCHDOG)
474 /* Initialise the Wathcdog values and reset it (if req) */
475 /*------------------------------------------------------*/
476 lis r4, CONFIG_SYS_WATCHDOG_VALUE
477 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
487 /* Disable Wathcdog */
488 /*-------------------*/
490 /* Check to see if its enabled for disabling
491 once disabled by SW you can't re-enable */
497 #endif /* CONFIG_WATCHDOG */
499 #if defined(CONFIG_MASK_AER_AO)
500 /* Write the Arbiter Event Enable to mask Address Only traps. */
501 /* This prevents the dcbz instruction from being trapped when */
502 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
503 /* COHERENCY bit is set in the WIMG bits, which is often */
504 /* needed for PCI operation. */
506 rlwinm r0, r4, 0, ~AER_AO
508 #endif /* CONFIG_MASK_AER_AO */
510 /* Initialize the Hardware Implementation-dependent Registers */
511 /* HID0 also contains cache control */
512 /* - force invalidation of data and instruction caches */
513 /*------------------------------------------------------*/
515 lis r3, CONFIG_SYS_HID0_INIT@h
516 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
520 lis r3, CONFIG_SYS_HID0_FINAL@h
521 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
525 lis r3, CONFIG_SYS_HID2@h
526 ori r3, r3, CONFIG_SYS_HID2@l
531 /*------------------------------*/
534 /* setup_bats - set them up to some initial state */
540 addis r4, r0, CONFIG_SYS_IBAT0L@h
541 ori r4, r4, CONFIG_SYS_IBAT0L@l
542 addis r3, r0, CONFIG_SYS_IBAT0U@h
543 ori r3, r3, CONFIG_SYS_IBAT0U@l
548 addis r4, r0, CONFIG_SYS_DBAT0L@h
549 ori r4, r4, CONFIG_SYS_DBAT0L@l
550 addis r3, r0, CONFIG_SYS_DBAT0U@h
551 ori r3, r3, CONFIG_SYS_DBAT0U@l
556 addis r4, r0, CONFIG_SYS_IBAT1L@h
557 ori r4, r4, CONFIG_SYS_IBAT1L@l
558 addis r3, r0, CONFIG_SYS_IBAT1U@h
559 ori r3, r3, CONFIG_SYS_IBAT1U@l
564 addis r4, r0, CONFIG_SYS_DBAT1L@h
565 ori r4, r4, CONFIG_SYS_DBAT1L@l
566 addis r3, r0, CONFIG_SYS_DBAT1U@h
567 ori r3, r3, CONFIG_SYS_DBAT1U@l
572 addis r4, r0, CONFIG_SYS_IBAT2L@h
573 ori r4, r4, CONFIG_SYS_IBAT2L@l
574 addis r3, r0, CONFIG_SYS_IBAT2U@h
575 ori r3, r3, CONFIG_SYS_IBAT2U@l
580 addis r4, r0, CONFIG_SYS_DBAT2L@h
581 ori r4, r4, CONFIG_SYS_DBAT2L@l
582 addis r3, r0, CONFIG_SYS_DBAT2U@h
583 ori r3, r3, CONFIG_SYS_DBAT2U@l
588 addis r4, r0, CONFIG_SYS_IBAT3L@h
589 ori r4, r4, CONFIG_SYS_IBAT3L@l
590 addis r3, r0, CONFIG_SYS_IBAT3U@h
591 ori r3, r3, CONFIG_SYS_IBAT3U@l
596 addis r4, r0, CONFIG_SYS_DBAT3L@h
597 ori r4, r4, CONFIG_SYS_DBAT3L@l
598 addis r3, r0, CONFIG_SYS_DBAT3U@h
599 ori r3, r3, CONFIG_SYS_DBAT3U@l
603 #ifdef CONFIG_HIGH_BATS
605 addis r4, r0, CONFIG_SYS_IBAT4L@h
606 ori r4, r4, CONFIG_SYS_IBAT4L@l
607 addis r3, r0, CONFIG_SYS_IBAT4U@h
608 ori r3, r3, CONFIG_SYS_IBAT4U@l
613 addis r4, r0, CONFIG_SYS_DBAT4L@h
614 ori r4, r4, CONFIG_SYS_DBAT4L@l
615 addis r3, r0, CONFIG_SYS_DBAT4U@h
616 ori r3, r3, CONFIG_SYS_DBAT4U@l
621 addis r4, r0, CONFIG_SYS_IBAT5L@h
622 ori r4, r4, CONFIG_SYS_IBAT5L@l
623 addis r3, r0, CONFIG_SYS_IBAT5U@h
624 ori r3, r3, CONFIG_SYS_IBAT5U@l
629 addis r4, r0, CONFIG_SYS_DBAT5L@h
630 ori r4, r4, CONFIG_SYS_DBAT5L@l
631 addis r3, r0, CONFIG_SYS_DBAT5U@h
632 ori r3, r3, CONFIG_SYS_DBAT5U@l
637 addis r4, r0, CONFIG_SYS_IBAT6L@h
638 ori r4, r4, CONFIG_SYS_IBAT6L@l
639 addis r3, r0, CONFIG_SYS_IBAT6U@h
640 ori r3, r3, CONFIG_SYS_IBAT6U@l
645 addis r4, r0, CONFIG_SYS_DBAT6L@h
646 ori r4, r4, CONFIG_SYS_DBAT6L@l
647 addis r3, r0, CONFIG_SYS_DBAT6U@h
648 ori r3, r3, CONFIG_SYS_DBAT6U@l
653 addis r4, r0, CONFIG_SYS_IBAT7L@h
654 ori r4, r4, CONFIG_SYS_IBAT7L@l
655 addis r3, r0, CONFIG_SYS_IBAT7U@h
656 ori r3, r3, CONFIG_SYS_IBAT7U@l
661 addis r4, r0, CONFIG_SYS_DBAT7L@h
662 ori r4, r4, CONFIG_SYS_DBAT7L@l
663 addis r3, r0, CONFIG_SYS_DBAT7U@h
664 ori r3, r3, CONFIG_SYS_DBAT7U@l
671 /* invalidate all tlb's
673 * From the 603e User Manual: "The 603e provides the ability to
674 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
675 * instruction invalidates the TLB entry indexed by the EA, and
676 * operates on both the instruction and data TLBs simultaneously
677 * invalidating four TLB entries (both sets in each TLB). The
678 * index corresponds to bits 15-19 of the EA. To invalidate all
679 * entries within both TLBs, 32 tlbie instructions should be
680 * issued, incrementing this field by one each time."
682 * "Note that the tlbia instruction is not implemented on the
685 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
686 * incrementing by 0x1000 each time. The code below is sort of
687 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
701 .globl enable_addr_trans
703 /* enable address translation */
705 ori r5, r5, (MSR_IR | MSR_DR)
710 .globl disable_addr_trans
712 /* disable address translation */
715 andi. r0, r3, (MSR_IR | MSR_DR)
724 * Note: requires that all cache bits in
725 * HID0 are in the low half word.
731 li r4, HID0_ICFI|HID0_ILOCK
733 ori r4, r3, HID0_ICFI
735 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
737 mtspr HID0, r3 /* clears invalidate */
740 .globl icache_disable
744 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
747 mtspr HID0, r3 /* clears invalidate, enable and lock */
753 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
759 li r5, HID0_DCFI|HID0_DLOCK
763 mtspr HID0, r3 /* enable, no invalidate */
766 .globl dcache_disable
769 bl flush_dcache /* uses r3 and r5 */
771 li r5, HID0_DCE|HID0_DLOCK
773 ori r5, r3, HID0_DCFI
775 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
777 mtspr HID0, r3 /* clears invalidate */
784 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
790 lis r5, CONFIG_SYS_CACHELINE_SIZE
794 lis r5, CONFIG_SYS_CACHELINE_SIZE
816 /*-------------------------------------------------------------------*/
819 * void relocate_code (addr_sp, gd, addr_moni)
821 * This "function" does not return, instead it continues in RAM
822 * after relocating the monitor code.
826 * r5 = length in bytes
831 mr r1, r3 /* Set new stack pointer */
832 mr r9, r4 /* Save copy of Global Data pointer */
833 mr r10, r5 /* Save copy of Destination Address */
835 mr r3, r5 /* Destination Address */
836 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
837 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
838 lwz r5, GOT(__bss_start)
840 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
845 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
846 * + Destination Address
852 /* First our own GOT */
854 /* then the one used by the C code */
864 beq cr1,4f /* In place copy is not necessary */
865 beq 7f /* Protect against 0 count */
894 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
902 * Now flush the cache: note that we must start from a cache aligned
903 * address. Otherwise we might miss one cache line.
907 beq 7f /* Always flush prefetch queue in any case */
915 sync /* Wait for all dcbst to complete on bus */
921 7: sync /* Wait for all icbi to complete on bus */
925 * We are done. Do not return, instead branch to second part of board
926 * initialization, now running from RAM.
928 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
935 * Relocation Function, r14 point to got2+0x8000
937 * Adjust got2 pointers, no need to check for 0, this code
938 * already puts a few entries in the table.
940 li r0,__got2_entries@sectoff@l
941 la r3,GOT(_GOT2_TABLE_)
942 lwz r11,GOT(_GOT2_TABLE_)
951 #ifndef CONFIG_NAND_SPL
953 * Now adjust the fixups and the pointers to the fixups
954 * in case we need to move ourselves again.
956 2: li r0,__fixup_entries@sectoff@l
957 lwz r3,GOT(_FIXUP_TABLE_)
973 * Now clear BSS segment
975 lwz r3,GOT(__bss_start)
976 #if defined(CONFIG_HYMOD)
978 * For HYMOD - the environment is the very last item in flash.
979 * The real .bss stops just before environment starts, so only
980 * clear up to that point.
982 * taken from mods for FADS board
984 lwz r4,GOT(environment)
1000 mr r3, r9 /* Global Data pointer */
1001 mr r4, r10 /* Destination Address */
1004 #ifndef CONFIG_NAND_SPL
1006 * Copy exception vector code to low memory
1009 * r7: source address, r8: end address, r9: target address
1014 lwz r8, GOT(_end_of_vectors)
1016 li r9, 0x100 /* reset vector always at 0x100 */
1019 bgelr /* return if r7>=r8 - just in case */
1021 mflr r4 /* save link register */
1031 * relocate `hdlr' and `int_return' entries
1033 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1034 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1037 addi r7, r7, 0x100 /* next exception vector */
1041 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1044 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1047 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1048 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1051 addi r7, r7, 0x100 /* next exception vector */
1055 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1056 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1059 addi r7, r7, 0x100 /* next exception vector */
1063 mfmsr r3 /* now that the vectors have */
1064 lis r7, MSR_IP@h /* relocated into low memory */
1065 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1066 andc r3, r3, r7 /* (if it was on) */
1067 SYNC /* Some chip revs need this... */
1071 mtlr r4 /* restore link register */
1075 * Function: relocate entries for one exception vector
1078 lwz r0, 0(r7) /* hdlr ... */
1079 add r0, r0, r3 /* ... += dest_addr */
1082 lwz r0, 4(r7) /* int_return ... */
1083 add r0, r0, r3 /* ... += dest_addr */
1087 #endif /* !CONFIG_NAND_SPL */
1089 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1091 /* Allocate Initial RAM in data cache.
1093 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1094 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1095 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1096 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1103 /* Lock the data cache */
1105 ori r0, r0, HID0_DLOCK
1111 #ifndef CONFIG_NAND_SPL
1112 .globl unlock_ram_in_cache
1113 unlock_ram_in_cache:
1114 /* invalidate the INIT_RAM section */
1115 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1116 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1117 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1118 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1124 sync /* Wait for all icbi to complete on bus */
1127 /* Unlock the data cache and invalidate it */
1129 li r5, HID0_DLOCK|HID0_DCFI
1130 andc r3, r3, r5 /* no invalidate, unlock */
1131 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1133 mtspr HID0, r5 /* invalidate, unlock */
1135 mtspr HID0, r3 /* no invalidate, unlock */
1137 #endif /* !CONFIG_NAND_SPL */
1138 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1140 #ifdef CONFIG_SYS_FLASHBOOT
1142 /* When booting from ROM (Flash or EPROM), clear the */
1143 /* Address Mask in OR0 so ROM appears everywhere */
1144 /*----------------------------------------------------*/
1145 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1147 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1149 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1151 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1152 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1153 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1154 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1155 * 0xFF800. From the hard resetting to here, the processor fetched and
1156 * executed the instructions one by one. There is not absolutely
1157 * jumping happened. Laterly, the u-boot code has to do an absolutely
1158 * jumping to tell the CPU instruction fetching component what the
1159 * u-boot TEXT base address is. Because the TEXT base resides in the
1160 * boot ROM memory space, to garantee the code can run smoothly after
1161 * that jumping, we must map in the entire boot ROM by Local Access
1162 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1163 * address for boot ROM, such as 0xFE000000. In this case, the default
1164 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1165 * need another window to map in it.
1167 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1168 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1169 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1171 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1172 lis r4, (0x80000012)@h
1173 ori r4, r4, (0x80000012)@l
1174 li r5, CONFIG_SYS_FLASH_SIZE
1175 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1179 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1182 /* Though all the LBIU Local Access Windows and LBC Banks will be
1183 * initialized in the C code, we'd better configure boot ROM's
1184 * window 0 and bank 0 correctly at here.
1186 remap_flash_by_law0:
1187 /* Initialize the BR0 with the boot ROM starting address. */
1191 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1192 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1194 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1197 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1201 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1202 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1203 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1205 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1206 lis r4, (0x80000012)@h
1207 ori r4, r4, (0x80000012)@l
1208 li r5, CONFIG_SYS_FLASH_SIZE
1209 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1212 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1216 stw r4, LBLAWBAR1(r3)
1217 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1219 #endif /* CONFIG_SYS_FLASHBOOT */