2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
60 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
61 #define CONFIG_SYS_FLASHBOOT
65 * Set up GOT: Global Offset Table
67 * Use r14 to access the GOT
70 GOT_ENTRY(_GOT2_TABLE_)
71 GOT_ENTRY(__bss_start)
74 #ifndef CONFIG_NAND_SPL
75 GOT_ENTRY(_FIXUP_TABLE_)
77 GOT_ENTRY(_start_of_vectors)
78 GOT_ENTRY(_end_of_vectors)
79 GOT_ENTRY(transfer_to_handler)
84 * The Hard Reset Configuration Word (HRCW) table is in the first 64
85 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
86 * times so the processor can fetch it out of flash whether the flash
87 * is 8, 16, 32, or 64 bits wide (hardware trickery).
90 #define _HRCW_TABLE_ENTRY(w) \
91 .fill 8,1,(((w)>>24)&0xff); \
92 .fill 8,1,(((w)>>16)&0xff); \
93 .fill 8,1,(((w)>> 8)&0xff); \
94 .fill 8,1,(((w) )&0xff)
96 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
100 * Magic number and version string - put it after the HRCW since it
101 * cannot be first in flash like it is in many other processors.
103 .long 0x27051956 /* U-Boot Magic Number */
105 .globl version_string
107 .ascii U_BOOT_VERSION
108 .ascii " (", __DATE__, " - ", __TIME__, ")"
109 .ascii " ", CONFIG_IDENT_STRING, "\0"
112 #ifndef CONFIG_DEFAULT_IMMR
113 #error CONFIG_DEFAULT_IMMR must be defined
114 #endif /* CONFIG_SYS_DEFAULT_IMMR */
115 #ifndef CONFIG_SYS_IMMR
116 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
117 #endif /* CONFIG_SYS_IMMR */
120 * After configuration, a system reset exception is executed using the
121 * vector at offset 0x100 relative to the base set by MSR[IP]. If
122 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
123 * base address is 0xfff00000. In the case of a Power On Reset or Hard
124 * Reset, the value of MSR[IP] is determined by the CIP field in the
127 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
128 * This determines the location of the boot ROM (flash or EPROM) in the
129 * processor's address space at boot time. As long as the HRCW is set up
130 * so that we eventually end up executing the code below when the
131 * processor executes the reset exception, the actual values used should
134 * Once we have got here, the address mask in OR0 is cleared so that the
135 * bottom 32K of the boot ROM is effectively repeated all throughout the
136 * processor's address space, after which we can jump to the absolute
137 * address at which the boot ROM was linked at compile time, and proceed
138 * to initialise the memory controller without worrying if the rug will
139 * be pulled out from under us, so to speak (it will be fine as long as
140 * we configure BR0 with the same boot ROM link address).
142 . = EXC_OFF_SYS_RESET
145 _start: /* time t 0 */
146 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
150 . = EXC_OFF_SYS_RESET + 0x10
154 li r21, BOOTFLAG_WARM /* Software reboot */
158 boot_cold: /* time t 3 */
159 lis r4, CONFIG_DEFAULT_IMMR@h
161 boot_warm: /* time t 5 */
162 mfmsr r5 /* save msr contents */
163 lis r3, CONFIG_SYS_IMMR@h
164 ori r3, r3, CONFIG_SYS_IMMR@l
167 /* Initialise the E300 processor core */
168 /*------------------------------------------*/
170 #ifdef CONFIG_NAND_SPL
171 /* The FCM begins execution after only the first page
172 * is loaded. Wait for the rest before branching
173 * to another flash page.
184 #ifdef CONFIG_SYS_FLASHBOOT
186 /* Inflate flash location so it appears everywhere, calculate */
187 /* the absolute address in final location of the FLASH, jump */
188 /* there and deflate the flash size back to minimal size */
189 /*------------------------------------------------------------*/
191 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
192 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
193 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
197 #if 1 /* Remapping flash with LAW0. */
198 bl remap_flash_by_law0
200 #endif /* CONFIG_SYS_FLASHBOOT */
207 * Cache must be enabled here for stack-in-cache trick.
208 * This means we need to enable the BATS.
210 * 1) for the EVB, original gt regs need to be mapped
211 * 2) need to have an IBAT for the 0xf region,
212 * we are running there!
213 * Cache should be turned on after BATs, since by default
214 * everything is write-through.
215 * The init-mem BAT can be reused after reloc. The old
216 * gt-regs BAT can be reused after board_init_f calls
217 * board_early_init_f (EVB only).
219 /* enable address translation */
223 /* enable the data cache */
226 #ifdef CONFIG_SYS_INIT_RAM_LOCK
231 /* set up the stack pointer in our newly created
233 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
234 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
236 li r0, 0 /* Make room for stack frame header and */
237 stwu r0, -4(r1) /* clear final stack frame so that */
238 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
241 /* let the C-code set up the rest */
243 /* Be careful to keep code relocatable & stack humble */
244 /*------------------------------------------------------*/
246 GET_GOT /* initialize GOT access */
249 lis r3, CONFIG_SYS_IMMR@h
250 /* run low-level CPU init code (in Flash)*/
255 /* run 1st part of board init code (in Flash)*/
258 #ifndef CONFIG_NAND_SPL
263 .globl _start_of_vectors
267 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
269 /* Data Storage exception. */
270 STD_EXCEPTION(0x300, DataStorage, UnknownException)
272 /* Instruction Storage exception. */
273 STD_EXCEPTION(0x400, InstStorage, UnknownException)
275 /* External Interrupt exception. */
277 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
280 /* Alignment exception. */
283 EXCEPTION_PROLOG(SRR0, SRR1)
288 addi r3,r1,STACK_FRAME_OVERHEAD
290 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
291 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
292 lwz r6,GOT(transfer_to_handler)
296 .long AlignmentException - _start + EXC_OFF_SYS_RESET
297 .long int_return - _start + EXC_OFF_SYS_RESET
299 /* Program check exception */
302 EXCEPTION_PROLOG(SRR0, SRR1)
303 addi r3,r1,STACK_FRAME_OVERHEAD
305 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
306 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
307 lwz r6,GOT(transfer_to_handler)
311 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
312 .long int_return - _start + EXC_OFF_SYS_RESET
314 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
316 /* I guess we could implement decrementer, and may have
317 * to someday for timekeeping.
319 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
321 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
322 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
323 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
324 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
326 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
327 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
329 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
330 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
331 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
335 * This exception occurs when the program counter matches the
336 * Instruction Address Breakpoint Register (IABR).
338 * I want the cpu to halt if this occurs so I can hunt around
339 * with the debugger and look at things.
341 * When DEBUG is defined, both machine check enable (in the MSR)
342 * and checkstop reset enable (in the reset mode register) are
343 * turned off and so a checkstop condition will result in the cpu
346 * I force the cpu into a checkstop condition by putting an illegal
347 * instruction here (at least this is the theory).
349 * well - that didnt work, so just do an infinite loop!
353 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
355 STD_EXCEPTION(0x1400, SMI, UnknownException)
357 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
358 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
359 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
360 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
361 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
362 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
363 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
364 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
365 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
366 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
367 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
368 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
369 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
370 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
371 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
372 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
373 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
374 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
375 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
376 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
377 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
378 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
379 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
380 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
381 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
382 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
383 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
386 .globl _end_of_vectors
392 * This code finishes saving the registers to the exception frame
393 * and jumps to the appropriate handler for the exception.
394 * Register r21 is pointer into trap frame, r1 has new stack pointer.
396 .globl transfer_to_handler
407 andi. r24,r23,0x3f00 /* get vector offset */
411 lwz r24,0(r23) /* virtual address of handler */
412 lwz r23,4(r23) /* where to go when done */
417 rfi /* jump to handler, enable MMU */
420 mfmsr r28 /* Disable interrupts */
424 SYNC /* Some chip revs need this... */
439 lwz r2,_NIP(r1) /* Restore environment */
448 #endif /* !CONFIG_NAND_SPL */
451 * This code initialises the E300 processor core
452 * (conforms to PowerPC 603e spec)
453 * Note: expects original MSR contents to be in r5.
455 .globl init_e300_core
456 init_e300_core: /* time t 10 */
457 /* Initialize machine status; enable machine check interrupt */
458 /*-----------------------------------------------------------*/
460 li r3, MSR_KERNEL /* Set ME and RI flags */
461 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
463 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
465 SYNC /* Some chip revs need this... */
468 mtspr SRR1, r3 /* Make SRR1 match MSR */
471 lis r3, CONFIG_SYS_IMMR@h
472 #if defined(CONFIG_WATCHDOG)
473 /* Initialise the Wathcdog values and reset it (if req) */
474 /*------------------------------------------------------*/
475 lis r4, CONFIG_SYS_WATCHDOG_VALUE
476 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
486 /* Disable Wathcdog */
487 /*-------------------*/
489 /* Check to see if its enabled for disabling
490 once disabled by SW you can't re-enable */
496 #endif /* CONFIG_WATCHDOG */
498 #if defined(CONFIG_MASK_AER_AO)
499 /* Write the Arbiter Event Enable to mask Address Only traps. */
500 /* This prevents the dcbz instruction from being trapped when */
501 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
502 /* COHERENCY bit is set in the WIMG bits, which is often */
503 /* needed for PCI operation. */
505 rlwinm r0, r4, 0, ~AER_AO
507 #endif /* CONFIG_MASK_AER_AO */
509 /* Initialize the Hardware Implementation-dependent Registers */
510 /* HID0 also contains cache control */
511 /* - force invalidation of data and instruction caches */
512 /*------------------------------------------------------*/
514 lis r3, CONFIG_SYS_HID0_INIT@h
515 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
519 lis r3, CONFIG_SYS_HID0_FINAL@h
520 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
524 lis r3, CONFIG_SYS_HID2@h
525 ori r3, r3, CONFIG_SYS_HID2@l
530 /*------------------------------*/
533 /* setup_bats - set them up to some initial state */
539 addis r4, r0, CONFIG_SYS_IBAT0L@h
540 ori r4, r4, CONFIG_SYS_IBAT0L@l
541 addis r3, r0, CONFIG_SYS_IBAT0U@h
542 ori r3, r3, CONFIG_SYS_IBAT0U@l
547 addis r4, r0, CONFIG_SYS_DBAT0L@h
548 ori r4, r4, CONFIG_SYS_DBAT0L@l
549 addis r3, r0, CONFIG_SYS_DBAT0U@h
550 ori r3, r3, CONFIG_SYS_DBAT0U@l
555 addis r4, r0, CONFIG_SYS_IBAT1L@h
556 ori r4, r4, CONFIG_SYS_IBAT1L@l
557 addis r3, r0, CONFIG_SYS_IBAT1U@h
558 ori r3, r3, CONFIG_SYS_IBAT1U@l
563 addis r4, r0, CONFIG_SYS_DBAT1L@h
564 ori r4, r4, CONFIG_SYS_DBAT1L@l
565 addis r3, r0, CONFIG_SYS_DBAT1U@h
566 ori r3, r3, CONFIG_SYS_DBAT1U@l
571 addis r4, r0, CONFIG_SYS_IBAT2L@h
572 ori r4, r4, CONFIG_SYS_IBAT2L@l
573 addis r3, r0, CONFIG_SYS_IBAT2U@h
574 ori r3, r3, CONFIG_SYS_IBAT2U@l
579 addis r4, r0, CONFIG_SYS_DBAT2L@h
580 ori r4, r4, CONFIG_SYS_DBAT2L@l
581 addis r3, r0, CONFIG_SYS_DBAT2U@h
582 ori r3, r3, CONFIG_SYS_DBAT2U@l
587 addis r4, r0, CONFIG_SYS_IBAT3L@h
588 ori r4, r4, CONFIG_SYS_IBAT3L@l
589 addis r3, r0, CONFIG_SYS_IBAT3U@h
590 ori r3, r3, CONFIG_SYS_IBAT3U@l
595 addis r4, r0, CONFIG_SYS_DBAT3L@h
596 ori r4, r4, CONFIG_SYS_DBAT3L@l
597 addis r3, r0, CONFIG_SYS_DBAT3U@h
598 ori r3, r3, CONFIG_SYS_DBAT3U@l
602 #ifdef CONFIG_HIGH_BATS
604 addis r4, r0, CONFIG_SYS_IBAT4L@h
605 ori r4, r4, CONFIG_SYS_IBAT4L@l
606 addis r3, r0, CONFIG_SYS_IBAT4U@h
607 ori r3, r3, CONFIG_SYS_IBAT4U@l
612 addis r4, r0, CONFIG_SYS_DBAT4L@h
613 ori r4, r4, CONFIG_SYS_DBAT4L@l
614 addis r3, r0, CONFIG_SYS_DBAT4U@h
615 ori r3, r3, CONFIG_SYS_DBAT4U@l
620 addis r4, r0, CONFIG_SYS_IBAT5L@h
621 ori r4, r4, CONFIG_SYS_IBAT5L@l
622 addis r3, r0, CONFIG_SYS_IBAT5U@h
623 ori r3, r3, CONFIG_SYS_IBAT5U@l
628 addis r4, r0, CONFIG_SYS_DBAT5L@h
629 ori r4, r4, CONFIG_SYS_DBAT5L@l
630 addis r3, r0, CONFIG_SYS_DBAT5U@h
631 ori r3, r3, CONFIG_SYS_DBAT5U@l
636 addis r4, r0, CONFIG_SYS_IBAT6L@h
637 ori r4, r4, CONFIG_SYS_IBAT6L@l
638 addis r3, r0, CONFIG_SYS_IBAT6U@h
639 ori r3, r3, CONFIG_SYS_IBAT6U@l
644 addis r4, r0, CONFIG_SYS_DBAT6L@h
645 ori r4, r4, CONFIG_SYS_DBAT6L@l
646 addis r3, r0, CONFIG_SYS_DBAT6U@h
647 ori r3, r3, CONFIG_SYS_DBAT6U@l
652 addis r4, r0, CONFIG_SYS_IBAT7L@h
653 ori r4, r4, CONFIG_SYS_IBAT7L@l
654 addis r3, r0, CONFIG_SYS_IBAT7U@h
655 ori r3, r3, CONFIG_SYS_IBAT7U@l
660 addis r4, r0, CONFIG_SYS_DBAT7L@h
661 ori r4, r4, CONFIG_SYS_DBAT7L@l
662 addis r3, r0, CONFIG_SYS_DBAT7U@h
663 ori r3, r3, CONFIG_SYS_DBAT7U@l
670 /* invalidate all tlb's
672 * From the 603e User Manual: "The 603e provides the ability to
673 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
674 * instruction invalidates the TLB entry indexed by the EA, and
675 * operates on both the instruction and data TLBs simultaneously
676 * invalidating four TLB entries (both sets in each TLB). The
677 * index corresponds to bits 15-19 of the EA. To invalidate all
678 * entries within both TLBs, 32 tlbie instructions should be
679 * issued, incrementing this field by one each time."
681 * "Note that the tlbia instruction is not implemented on the
684 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
685 * incrementing by 0x1000 each time. The code below is sort of
686 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
700 .globl enable_addr_trans
702 /* enable address translation */
704 ori r5, r5, (MSR_IR | MSR_DR)
709 .globl disable_addr_trans
711 /* disable address translation */
714 andi. r0, r3, (MSR_IR | MSR_DR)
723 * Note: requires that all cache bits in
724 * HID0 are in the low half word.
730 li r4, HID0_ICFI|HID0_ILOCK
732 ori r4, r3, HID0_ICFI
734 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
736 mtspr HID0, r3 /* clears invalidate */
739 .globl icache_disable
743 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
746 mtspr HID0, r3 /* clears invalidate, enable and lock */
752 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
758 li r5, HID0_DCFI|HID0_DLOCK
762 mtspr HID0, r3 /* enable, no invalidate */
765 .globl dcache_disable
768 bl flush_dcache /* uses r3 and r5 */
770 li r5, HID0_DCE|HID0_DLOCK
772 ori r5, r3, HID0_DCFI
774 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
776 mtspr HID0, r3 /* clears invalidate */
783 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
789 lis r5, CONFIG_SYS_CACHELINE_SIZE
793 lis r5, CONFIG_SYS_CACHELINE_SIZE
815 /*-------------------------------------------------------------------*/
818 * void relocate_code (addr_sp, gd, addr_moni)
820 * This "function" does not return, instead it continues in RAM
821 * after relocating the monitor code.
825 * r5 = length in bytes
830 mr r1, r3 /* Set new stack pointer */
831 mr r9, r4 /* Save copy of Global Data pointer */
832 mr r10, r5 /* Save copy of Destination Address */
834 mr r3, r5 /* Destination Address */
835 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
836 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
837 lwz r5, GOT(__bss_start)
839 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
844 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
845 * + Destination Address
851 /* First our own GOT */
853 /* then the one used by the C code */
863 beq cr1,4f /* In place copy is not necessary */
864 beq 7f /* Protect against 0 count */
893 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
901 * Now flush the cache: note that we must start from a cache aligned
902 * address. Otherwise we might miss one cache line.
906 beq 7f /* Always flush prefetch queue in any case */
914 sync /* Wait for all dcbst to complete on bus */
920 7: sync /* Wait for all icbi to complete on bus */
924 * We are done. Do not return, instead branch to second part of board
925 * initialization, now running from RAM.
927 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
934 * Relocation Function, r14 point to got2+0x8000
936 * Adjust got2 pointers, no need to check for 0, this code
937 * already puts a few entries in the table.
939 li r0,__got2_entries@sectoff@l
940 la r3,GOT(_GOT2_TABLE_)
941 lwz r11,GOT(_GOT2_TABLE_)
950 #ifndef CONFIG_NAND_SPL
952 * Now adjust the fixups and the pointers to the fixups
953 * in case we need to move ourselves again.
955 2: li r0,__fixup_entries@sectoff@l
956 lwz r3,GOT(_FIXUP_TABLE_)
972 * Now clear BSS segment
974 lwz r3,GOT(__bss_start)
975 #if defined(CONFIG_HYMOD)
977 * For HYMOD - the environment is the very last item in flash.
978 * The real .bss stops just before environment starts, so only
979 * clear up to that point.
981 * taken from mods for FADS board
983 lwz r4,GOT(environment)
999 mr r3, r9 /* Global Data pointer */
1000 mr r4, r10 /* Destination Address */
1003 #ifndef CONFIG_NAND_SPL
1005 * Copy exception vector code to low memory
1008 * r7: source address, r8: end address, r9: target address
1013 lwz r8, GOT(_end_of_vectors)
1015 li r9, 0x100 /* reset vector always at 0x100 */
1018 bgelr /* return if r7>=r8 - just in case */
1020 mflr r4 /* save link register */
1030 * relocate `hdlr' and `int_return' entries
1032 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1033 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1036 addi r7, r7, 0x100 /* next exception vector */
1040 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1043 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1046 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1047 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1050 addi r7, r7, 0x100 /* next exception vector */
1054 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1055 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1058 addi r7, r7, 0x100 /* next exception vector */
1062 mfmsr r3 /* now that the vectors have */
1063 lis r7, MSR_IP@h /* relocated into low memory */
1064 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1065 andc r3, r3, r7 /* (if it was on) */
1066 SYNC /* Some chip revs need this... */
1070 mtlr r4 /* restore link register */
1074 * Function: relocate entries for one exception vector
1077 lwz r0, 0(r7) /* hdlr ... */
1078 add r0, r0, r3 /* ... += dest_addr */
1081 lwz r0, 4(r7) /* int_return ... */
1082 add r0, r0, r3 /* ... += dest_addr */
1086 #endif /* !CONFIG_NAND_SPL */
1088 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1090 /* Allocate Initial RAM in data cache.
1092 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1093 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1094 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1095 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1102 /* Lock the data cache */
1104 ori r0, r0, HID0_DLOCK
1110 #ifndef CONFIG_NAND_SPL
1111 .globl unlock_ram_in_cache
1112 unlock_ram_in_cache:
1113 /* invalidate the INIT_RAM section */
1114 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1115 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1116 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1117 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1123 sync /* Wait for all icbi to complete on bus */
1126 /* Unlock the data cache and invalidate it */
1128 li r5, HID0_DLOCK|HID0_DCFI
1129 andc r3, r3, r5 /* no invalidate, unlock */
1130 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1132 mtspr HID0, r5 /* invalidate, unlock */
1134 mtspr HID0, r3 /* no invalidate, unlock */
1136 #endif /* !CONFIG_NAND_SPL */
1137 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1139 #ifdef CONFIG_SYS_FLASHBOOT
1141 /* When booting from ROM (Flash or EPROM), clear the */
1142 /* Address Mask in OR0 so ROM appears everywhere */
1143 /*----------------------------------------------------*/
1144 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1146 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1148 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1150 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1151 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1152 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1153 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1154 * 0xFF800. From the hard resetting to here, the processor fetched and
1155 * executed the instructions one by one. There is not absolutely
1156 * jumping happened. Laterly, the u-boot code has to do an absolutely
1157 * jumping to tell the CPU instruction fetching component what the
1158 * u-boot TEXT base address is. Because the TEXT base resides in the
1159 * boot ROM memory space, to garantee the code can run smoothly after
1160 * that jumping, we must map in the entire boot ROM by Local Access
1161 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1162 * address for boot ROM, such as 0xFE000000. In this case, the default
1163 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1164 * need another window to map in it.
1166 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1167 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1168 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1170 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1171 lis r4, (0x80000012)@h
1172 ori r4, r4, (0x80000012)@l
1173 li r5, CONFIG_SYS_FLASH_SIZE
1174 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1178 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1181 /* Though all the LBIU Local Access Windows and LBC Banks will be
1182 * initialized in the C code, we'd better configure boot ROM's
1183 * window 0 and bank 0 correctly at here.
1185 remap_flash_by_law0:
1186 /* Initialize the BR0 with the boot ROM starting address. */
1190 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1191 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1193 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1196 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1200 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1201 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1202 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1204 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1205 lis r4, (0x80000012)@h
1206 ori r4, r4, (0x80000012)@l
1207 li r5, CONFIG_SYS_FLASH_SIZE
1208 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1211 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1215 stw r4, LBLAWBAR1(r3)
1216 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1218 #endif /* CONFIG_SYS_FLASHBOOT */