2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 /* ----------------------------------------------------------------- */
50 mult_t core_csb_ratio;
54 corecnf_t corecnf_tab[] = {
55 {_byp, _byp}, /* 0x00 */
56 {_byp, _byp}, /* 0x01 */
57 {_byp, _byp}, /* 0x02 */
58 {_byp, _byp}, /* 0x03 */
59 {_byp, _byp}, /* 0x04 */
60 {_byp, _byp}, /* 0x05 */
61 {_byp, _byp}, /* 0x06 */
62 {_byp, _byp}, /* 0x07 */
63 {_1x, _x2}, /* 0x08 */
64 {_1x, _x4}, /* 0x09 */
65 {_1x, _x8}, /* 0x0A */
66 {_1x, _x8}, /* 0x0B */
67 {_1_5x, _x2}, /* 0x0C */
68 {_1_5x, _x4}, /* 0x0D */
69 {_1_5x, _x8}, /* 0x0E */
70 {_1_5x, _x8}, /* 0x0F */
71 {_2x, _x2}, /* 0x10 */
72 {_2x, _x4}, /* 0x11 */
73 {_2x, _x8}, /* 0x12 */
74 {_2x, _x8}, /* 0x13 */
75 {_2_5x, _x2}, /* 0x14 */
76 {_2_5x, _x4}, /* 0x15 */
77 {_2_5x, _x8}, /* 0x16 */
78 {_2_5x, _x8}, /* 0x17 */
79 {_3x, _x2}, /* 0x18 */
80 {_3x, _x4}, /* 0x19 */
81 {_3x, _x8}, /* 0x1A */
82 {_3x, _x8}, /* 0x1B */
85 /* ----------------------------------------------------------------- */
92 volatile immap_t *im = (immap_t *) CFG_IMMR;
97 u32 corecnf_tab_index;
102 #if defined(CONFIG_MPC834X)
110 #if !defined(CONFIG_MPC832X)
117 #if defined(CONFIG_MPC8360)
120 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
127 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
130 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
132 if (im->reset.rcwh & HRCWH_PCI_HOST) {
133 #if defined(CONFIG_83XX_CLKIN)
134 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
136 pci_sync_in = 0xDEADBEEF;
139 #if defined(CONFIG_83XX_PCICLK)
140 pci_sync_in = CONFIG_83XX_PCICLK;
142 pci_sync_in = 0xDEADBEEF;
146 spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
147 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
151 #if defined(CONFIG_MPC834X)
152 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
160 tsec1_clk = csb_clk / 2;
163 tsec1_clk = csb_clk / 3;
166 /* unkown SCCR_TSEC1CM value */
170 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
178 tsec2_clk = csb_clk / 2;
181 tsec2_clk = csb_clk / 3;
184 /* unkown SCCR_TSEC2CM value */
188 i2c1_clk = tsec2_clk;
190 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
195 usbmph_clk = csb_clk;
198 usbmph_clk = csb_clk / 2;
201 usbmph_clk = csb_clk / 3;
204 /* unkown SCCR_USBMPHCM value */
208 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
216 usbdr_clk = csb_clk / 2;
219 usbdr_clk = csb_clk / 3;
222 /* unkown SCCR_USBDRCM value */
226 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
227 /* if USB MPH clock is not disabled and
228 * USB DR clock is not disabled then
229 * USB MPH & USB DR must have the same rate
234 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
237 #if !defined(CONFIG_MPC832X)
238 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
241 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
249 enc_clk = csb_clk / 2;
252 enc_clk = csb_clk / 3;
255 /* unkown SCCR_ENCCM value */
260 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
261 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
266 lclk_clk = lbiu_clk / lcrr;
274 (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
275 corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
276 #if defined(CONFIG_MPC8360)
277 ddr_sec_clk = csb_clk * (1 +
278 ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
281 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
282 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
283 /* corecnf_tab_index is too high, possibly worng value */
286 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
293 core_clk = (3 * csb_clk) / 2;
296 core_clk = 2 * csb_clk;
299 core_clk = (5 * csb_clk) / 2;
302 core_clk = 3 * csb_clk;
305 /* unkown core to csb ratio */
309 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
310 qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
311 qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
312 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
313 brg_clk = qe_clk / 2;
316 gd->csb_clk = csb_clk;
317 #if defined(CONFIG_MPC834X)
318 gd->tsec1_clk = tsec1_clk;
319 gd->tsec2_clk = tsec2_clk;
320 gd->usbmph_clk = usbmph_clk;
321 gd->usbdr_clk = usbdr_clk;
323 gd->core_clk = core_clk;
324 gd->i2c1_clk = i2c1_clk;
325 #if !defined(CONFIG_MPC832X)
326 gd->i2c2_clk = i2c2_clk;
328 gd->enc_clk = enc_clk;
329 gd->lbiu_clk = lbiu_clk;
330 gd->lclk_clk = lclk_clk;
331 gd->ddr_clk = ddr_clk;
332 #if defined(CONFIG_MPC8360)
333 gd->ddr_sec_clk = ddr_sec_clk;
335 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
337 gd->brg_clk = brg_clk;
339 gd->cpu_clk = gd->core_clk;
340 gd->bus_clk = gd->csb_clk;
345 /********************************************
347 * return system bus freq in Hz
348 *********************************************/
349 ulong get_bus_freq(ulong dummy)
354 int print_clock_conf(void)
356 printf("Clock configuration:\n");
357 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
358 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
359 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
360 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
361 printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
363 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
364 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
365 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
366 #if defined(CONFIG_MPC8360)
367 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
369 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
370 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
371 #if !defined(CONFIG_MPC832X)
372 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
374 #if defined(CONFIG_MPC834X)
375 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
376 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
377 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
378 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);