2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 /* ----------------------------------------------------------------- */
50 mult_t core_csb_ratio;
54 corecnf_t corecnf_tab[] = {
55 {_byp, _byp}, /* 0x00 */
56 {_byp, _byp}, /* 0x01 */
57 {_byp, _byp}, /* 0x02 */
58 {_byp, _byp}, /* 0x03 */
59 {_byp, _byp}, /* 0x04 */
60 {_byp, _byp}, /* 0x05 */
61 {_byp, _byp}, /* 0x06 */
62 {_byp, _byp}, /* 0x07 */
63 {_1x, _x2}, /* 0x08 */
64 {_1x, _x4}, /* 0x09 */
65 {_1x, _x8}, /* 0x0A */
66 {_1x, _x8}, /* 0x0B */
67 {_1_5x, _x2}, /* 0x0C */
68 {_1_5x, _x4}, /* 0x0D */
69 {_1_5x, _x8}, /* 0x0E */
70 {_1_5x, _x8}, /* 0x0F */
71 {_2x, _x2}, /* 0x10 */
72 {_2x, _x4}, /* 0x11 */
73 {_2x, _x8}, /* 0x12 */
74 {_2x, _x8}, /* 0x13 */
75 {_2_5x, _x2}, /* 0x14 */
76 {_2_5x, _x4}, /* 0x15 */
77 {_2_5x, _x8}, /* 0x16 */
78 {_2_5x, _x8}, /* 0x17 */
79 {_3x, _x2}, /* 0x18 */
80 {_3x, _x4}, /* 0x19 */
81 {_3x, _x8}, /* 0x1A */
82 {_3x, _x8}, /* 0x1B */
85 /* ----------------------------------------------------------------- */
92 volatile immap_t *im = (immap_t *) CFG_IMMR;
97 u32 corecnf_tab_index;
102 #if defined(CONFIG_MPC8349)
115 #if defined (CONFIG_MPC8360)
123 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
126 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
128 if (im->reset.rcwh & HRCWH_PCI_HOST) {
129 #if defined(CONFIG_83XX_CLKIN)
130 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
132 pci_sync_in = 0xDEADBEEF;
135 #if defined(CONFIG_83XX_PCICLK)
136 pci_sync_in = CONFIG_83XX_PCICLK;
138 pci_sync_in = 0xDEADBEEF;
142 spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
143 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
147 #if defined(CONFIG_MPC8349)
148 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
156 tsec1_clk = csb_clk / 2;
159 tsec1_clk = csb_clk / 3;
162 /* unkown SCCR_TSEC1CM value */
166 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
174 tsec2_clk = csb_clk / 2;
177 tsec2_clk = csb_clk / 3;
180 /* unkown SCCR_TSEC2CM value */
184 i2c1_clk = tsec2_clk;
186 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
191 usbmph_clk = csb_clk;
194 usbmph_clk = csb_clk / 2;
197 usbmph_clk = csb_clk / 3;
200 /* unkown SCCR_USBMPHCM value */
204 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
212 usbdr_clk = csb_clk / 2;
215 usbdr_clk = csb_clk / 3;
218 /* unkown SCCR_USBDRCM value */
222 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
223 /* if USB MPH clock is not disabled and
224 * USB DR clock is not disabled then
225 * USB MPH & USB DR must have the same rate
230 #if defined (CONFIG_MPC8360)
233 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
235 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
243 enc_clk = csb_clk / 2;
246 enc_clk = csb_clk / 3;
249 /* unkown SCCR_ENCCM value */
252 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
254 (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
256 #error Unknown MPC83xx chip
258 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
263 lclk_clk = lbiu_clk / lcrr;
269 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
271 (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
272 corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
273 #if defined (CONFIG_MPC8360)
274 ddr_sec_clk = csb_clk * (1 +
275 ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
278 #error Unknown MPC83xx chip
281 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
282 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
283 /* corecnf_tab_index is too high, possibly worng value */
286 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
293 core_clk = (3 * csb_clk) / 2;
296 core_clk = 2 * csb_clk;
299 core_clk = (5 * csb_clk) / 2;
302 core_clk = 3 * csb_clk;
305 /* unkown core to csb ratio */
309 #if defined (CONFIG_MPC8360)
310 qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
311 qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
312 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
313 brg_clk = qe_clk / 2;
316 gd->csb_clk = csb_clk;
317 #if defined(CONFIG_MPC8349)
318 gd->tsec1_clk = tsec1_clk;
319 gd->tsec2_clk = tsec2_clk;
320 gd->usbmph_clk = usbmph_clk;
321 gd->usbdr_clk = usbdr_clk;
323 gd->core_clk = core_clk;
324 gd->i2c1_clk = i2c1_clk;
325 gd->i2c2_clk = i2c2_clk;
326 gd->enc_clk = enc_clk;
327 gd->lbiu_clk = lbiu_clk;
328 gd->lclk_clk = lclk_clk;
329 gd->ddr_clk = ddr_clk;
330 #if defined (CONFIG_MPC8360)
331 gd->ddr_sec_clk = ddr_sec_clk;
333 gd->brg_clk = brg_clk;
335 gd->cpu_clk = gd->core_clk;
336 gd->bus_clk = gd->csb_clk;
341 /********************************************
343 * return system bus freq in Hz
344 *********************************************/
345 ulong get_bus_freq(ulong dummy)
350 int print_clock_conf(void)
352 printf("Clock configuration:\n");
353 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
354 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
355 #if defined (CONFIG_MPC8360)
356 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
358 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
359 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
360 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
361 #if defined (CONFIG_MPC8360)
362 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
364 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
365 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
366 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
367 #if defined(CONFIG_MPC8349)
368 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
369 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
370 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
371 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);