2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* ----------------------------------------------------------------- */
51 mult_t core_csb_ratio;
55 corecnf_t corecnf_tab[] = {
56 {_byp, _byp}, /* 0x00 */
57 {_byp, _byp}, /* 0x01 */
58 {_byp, _byp}, /* 0x02 */
59 {_byp, _byp}, /* 0x03 */
60 {_byp, _byp}, /* 0x04 */
61 {_byp, _byp}, /* 0x05 */
62 {_byp, _byp}, /* 0x06 */
63 {_byp, _byp}, /* 0x07 */
64 {_1x, _x2}, /* 0x08 */
65 {_1x, _x4}, /* 0x09 */
66 {_1x, _x8}, /* 0x0A */
67 {_1x, _x8}, /* 0x0B */
68 {_1_5x, _x2}, /* 0x0C */
69 {_1_5x, _x4}, /* 0x0D */
70 {_1_5x, _x8}, /* 0x0E */
71 {_1_5x, _x8}, /* 0x0F */
72 {_2x, _x2}, /* 0x10 */
73 {_2x, _x4}, /* 0x11 */
74 {_2x, _x8}, /* 0x12 */
75 {_2x, _x8}, /* 0x13 */
76 {_2_5x, _x2}, /* 0x14 */
77 {_2_5x, _x4}, /* 0x15 */
78 {_2_5x, _x8}, /* 0x16 */
79 {_2_5x, _x8}, /* 0x17 */
80 {_3x, _x2}, /* 0x18 */
81 {_3x, _x4}, /* 0x19 */
82 {_3x, _x8}, /* 0x1A */
83 {_3x, _x8}, /* 0x1B */
86 /* ----------------------------------------------------------------- */
93 volatile immap_t *im = (immap_t *) CFG_IMMR;
98 u32 corecnf_tab_index;
103 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
108 #ifdef CONFIG_MPC834X
113 #if !defined(CONFIG_MPC832X)
116 #if defined(CONFIG_MPC837X)
123 #if defined(CONFIG_MPC8360)
126 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
132 #if defined(CONFIG_MPC837X)
138 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
141 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
143 if (im->reset.rcwh & HRCWH_PCI_HOST) {
144 #if defined(CONFIG_83XX_CLKIN)
145 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
147 pci_sync_in = 0xDEADBEEF;
150 #if defined(CONFIG_83XX_PCICLK)
151 pci_sync_in = CONFIG_83XX_PCICLK;
153 pci_sync_in = 0xDEADBEEF;
157 spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
158 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
162 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
163 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
171 tsec1_clk = csb_clk / 2;
174 tsec1_clk = csb_clk / 3;
177 /* unkown SCCR_TSEC1CM value */
181 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
189 usbdr_clk = csb_clk / 2;
192 usbdr_clk = csb_clk / 3;
195 /* unkown SCCR_USBDRCM value */
200 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
201 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
209 tsec2_clk = csb_clk / 2;
212 tsec2_clk = csb_clk / 3;
215 /* unkown SCCR_TSEC2CM value */
218 #elif defined(CONFIG_MPC831X)
219 tsec2_clk = tsec1_clk;
221 if (!(sccr & SCCR_TSEC1ON))
223 if (!(sccr & SCCR_TSEC2ON))
227 #if defined(CONFIG_MPC834X)
228 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
233 usbmph_clk = csb_clk;
236 usbmph_clk = csb_clk / 2;
239 usbmph_clk = csb_clk / 3;
242 /* unkown SCCR_USBMPHCM value */
246 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
247 /* if USB MPH clock is not disabled and
248 * USB DR clock is not disabled then
249 * USB MPH & USB DR must have the same rate
254 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
262 enc_clk = csb_clk / 2;
265 enc_clk = csb_clk / 3;
268 /* unkown SCCR_ENCCM value */
272 #if defined(CONFIG_MPC837X)
273 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
281 sdhc_clk = csb_clk / 2;
284 sdhc_clk = csb_clk / 3;
287 /* unkown SCCR_SDHCCM value */
292 #if defined(CONFIG_MPC834X)
293 i2c1_clk = tsec2_clk;
294 #elif defined(CONFIG_MPC8360)
296 #elif defined(CONFIG_MPC832X)
298 #elif defined(CONFIG_MPC831X)
300 #elif defined(CONFIG_MPC837X)
303 #if !defined(CONFIG_MPC832X)
304 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
307 #if defined(CONFIG_MPC837X)
308 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
313 pciexp1_clk = csb_clk;
316 pciexp1_clk = csb_clk / 2;
319 pciexp1_clk = csb_clk / 3;
322 /* unkown SCCR_PCIEXP1CM value */
326 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
331 pciexp2_clk = csb_clk;
334 pciexp2_clk = csb_clk / 2;
337 pciexp2_clk = csb_clk / 3;
340 /* unkown SCCR_PCIEXP2CM value */
345 #if defined(CONFIG_MPC837X)
346 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
354 sata_clk = csb_clk / 2;
357 sata_clk = csb_clk / 3;
360 /* unkown SCCR_SATA1CM value */
366 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
367 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
372 lclk_clk = lbiu_clk / lcrr;
380 (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
381 corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
382 #if defined(CONFIG_MPC8360)
383 ddr_sec_clk = csb_clk * (1 +
384 ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
387 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
388 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
389 /* corecnf_tab_index is too high, possibly worng value */
392 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
399 core_clk = (3 * csb_clk) / 2;
402 core_clk = 2 * csb_clk;
405 core_clk = (5 * csb_clk) / 2;
408 core_clk = 3 * csb_clk;
411 /* unkown core to csb ratio */
415 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
416 qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
417 qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
418 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
419 brg_clk = qe_clk / 2;
422 gd->csb_clk = csb_clk;
423 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
424 gd->tsec1_clk = tsec1_clk;
425 gd->tsec2_clk = tsec2_clk;
426 gd->usbdr_clk = usbdr_clk;
428 #if defined(CONFIG_MPC834X)
429 gd->usbmph_clk = usbmph_clk;
431 #if defined(CONFIG_MPC837X)
432 gd->sdhc_clk = sdhc_clk;
434 gd->core_clk = core_clk;
435 gd->i2c1_clk = i2c1_clk;
436 #if !defined(CONFIG_MPC832X)
437 gd->i2c2_clk = i2c2_clk;
439 gd->enc_clk = enc_clk;
440 gd->lbiu_clk = lbiu_clk;
441 gd->lclk_clk = lclk_clk;
442 gd->ddr_clk = ddr_clk;
443 #if defined(CONFIG_MPC8360)
444 gd->ddr_sec_clk = ddr_sec_clk;
446 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
448 gd->brg_clk = brg_clk;
450 #if defined(CONFIG_MPC837X)
451 gd->pciexp1_clk = pciexp1_clk;
452 gd->pciexp2_clk = pciexp2_clk;
453 gd->sata_clk = sata_clk;
455 gd->pci_clk = pci_sync_in;
456 gd->cpu_clk = gd->core_clk;
457 gd->bus_clk = gd->csb_clk;
462 /********************************************
464 * return system bus freq in Hz
465 *********************************************/
466 ulong get_bus_freq(ulong dummy)
471 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
473 printf("Clock configuration:\n");
474 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
475 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
476 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
477 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
478 printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
480 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
481 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
482 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
483 #if defined(CONFIG_MPC8360)
484 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
486 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
487 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
488 #if !defined(CONFIG_MPC832X)
489 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
491 #if defined(CONFIG_MPC837X)
492 printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
494 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
495 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
496 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
497 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
499 #if defined(CONFIG_MPC834X)
500 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
502 #if defined(CONFIG_MPC837X)
503 printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
504 printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
505 printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
510 U_BOOT_CMD(clocks, 1, 0, do_clocks,
511 "clocks - print clock configuration\n",