2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 void board_add_ram_info(int use_default)
39 volatile immap_t *immap = (immap_t *) CFG_IMMR;
40 volatile ddr83xx_t *ddr = &immap->ddr;
42 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
43 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
45 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
50 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
55 #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
57 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
61 #ifdef CONFIG_SPD_EEPROM
63 DECLARE_GLOBAL_DATA_PTR;
65 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
66 extern void dma_init(void);
67 extern uint dma_check(void);
68 extern int dma_xfer(void *dest, uint count, void *src);
72 #define CFG_READ_SPD i2c_read
76 * Convert picoseconds into clock cycles (rounding up if needed).
79 picos_to_clk(int picos)
81 unsigned int ddr_bus_clk;
84 ddr_bus_clk = gd->ddr_clk >> 1;
85 clks = picos / (1000000000 / (ddr_bus_clk / 1000));
86 if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
92 unsigned int banksize(unsigned char row_dens)
94 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
97 int read_spd(uint addr)
104 static void spd_debug(spd_eeprom_t *spd)
106 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
107 printf ("SPD size: %d\n", spd->info_size);
108 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
109 printf ("Memory type: %d\n", spd->mem_type);
110 printf ("Row addr: %d\n", spd->nrow_addr);
111 printf ("Column addr: %d\n", spd->ncol_addr);
112 printf ("# of rows: %d\n", spd->nrows);
113 printf ("Row density: %d\n", spd->row_dens);
114 printf ("# of banks: %d\n", spd->nbanks);
115 printf ("Data width: %d\n",
116 256 * spd->dataw_msb + spd->dataw_lsb);
117 printf ("Chip width: %d\n", spd->primw);
118 printf ("Refresh rate: %02X\n", spd->refresh);
119 printf ("CAS latencies: %02X\n", spd->cas_lat);
120 printf ("Write latencies: %02X\n", spd->write_lat);
121 printf ("tRP: %d\n", spd->trp);
122 printf ("tRCD: %d\n", spd->trcd);
125 #endif /* SPD_DEBUG */
129 volatile immap_t *immap = (immap_t *)CFG_IMMR;
130 volatile ddr83xx_t *ddr = &immap->ddr;
131 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
133 unsigned int n_ranks;
134 unsigned int odt_rd_cfg, odt_wr_cfg;
135 unsigned char twr_clk, twtr_clk;
136 unsigned int sdram_type;
137 unsigned int memsize;
138 unsigned int law_size;
139 unsigned char caslat, caslat_ctrl;
140 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
141 unsigned int trcd_clk, trtp_clk;
142 unsigned char cke_min_clk;
143 unsigned char add_lat, wr_lat;
144 unsigned char wr_data_delay;
145 unsigned char four_act;
147 unsigned char burstlen;
148 unsigned char odt_cfg, mode_odt_enable;
149 unsigned int max_bus_clk;
150 unsigned int max_data_rate, effective_data_rate;
151 unsigned int ddrc_clk;
152 unsigned int refresh_clk;
153 unsigned int sdram_cfg;
154 unsigned int ddrc_ecc_enable;
155 unsigned int pvr = get_pvr();
157 /* Read SPD parameters with I2C */
158 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
162 /* Check the memory type */
163 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
164 debug("DDR: Module mem type is %02X\n", spd.mem_type);
168 /* Check the number of physical bank */
169 if (spd.mem_type == SPD_MEMTYPE_DDR) {
172 n_ranks = (spd.nrows & 0x7) + 1;
176 printf("DDR: The number of physical bank is %02X\n", n_ranks);
180 /* Check if the number of row of the module is in the range of DDRC */
181 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
182 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
187 /* Check if the number of col of the module is in the range of DDRC */
188 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
189 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
194 #ifdef CFG_DDRCDR_VALUE
196 * Adjust DDR II IO voltage biasing. It just makes it work.
198 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
199 immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
205 * ODT configuration recommendation from DDR Controller Chapter.
207 odt_rd_cfg = 0; /* Never assert ODT */
208 odt_wr_cfg = 0; /* Never assert ODT */
209 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
210 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
213 /* Setup DDR chip select register */
214 #ifdef CFG_83XX_DDR_USES_CS0
215 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
216 ddr->cs_config[0] = ( 1 << 31
219 | (spd.nrow_addr - 12) << 8
220 | (spd.ncol_addr - 8) );
222 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
223 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
226 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
227 | ((banksize(spd.row_dens) >> 23) - 1) );
228 ddr->cs_config[1] = ( 1<<31
231 | (spd.nrow_addr-12) << 8
232 | (spd.ncol_addr-8) );
233 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
234 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
238 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
239 ddr->cs_config[2] = ( 1 << 31
242 | (spd.nrow_addr - 12) << 8
243 | (spd.ncol_addr - 8) );
245 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
246 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
249 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
250 | ((banksize(spd.row_dens) >> 23) - 1) );
251 ddr->cs_config[3] = ( 1<<31
254 | (spd.nrow_addr-12) << 8
255 | (spd.ncol_addr-8) );
256 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
257 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
262 * Figure out memory size in Megabytes.
264 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
267 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
269 law_size = 19 + __ilog2(memsize);
272 * Set up LAWBAR for all of DDR.
274 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
275 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
276 debug("DDR:bar=0x%08x\n", ecm->bar);
277 debug("DDR:ar=0x%08x\n", ecm->ar);
280 * Find the largest CAS by locating the highest 1 bit
281 * in the spd.cas_lat field. Translate it to a DDR
282 * controller field value:
284 * CAS Lat DDR I DDR II Ctrl
285 * Clocks SPD Bit SPD Bit Value
286 * ------- ------- ------- -----
297 caslat = __ilog2(spd.cas_lat);
298 if ((spd.mem_type == SPD_MEMTYPE_DDR)
300 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
302 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
303 && (caslat < 2 || caslat > 5)) {
304 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
308 debug("DDR: caslat SPD bit is %d\n", caslat);
310 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
311 + (spd.clk_cycle & 0x0f));
312 max_data_rate = max_bus_clk * 2;
314 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
316 ddrc_clk = gd->ddr_clk / 1000000;
317 effective_data_rate = 0;
319 if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
320 if (ddrc_clk <= 460 && ddrc_clk > 350) {
321 /* DDR controller clk at 350~460 */
322 effective_data_rate = 400; /* 5ns */
324 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
325 /* DDR controller clk at 280~350 */
326 effective_data_rate = 333; /* 6ns */
327 if (spd.clk_cycle2 == 0x60)
331 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
332 /* DDR controller clk at 230~280 */
333 effective_data_rate = 266; /* 7.5ns */
334 if (spd.clk_cycle3 == 0x75)
336 else if (spd.clk_cycle2 == 0x75)
340 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
341 /* DDR controller clk at 90~230 */
342 effective_data_rate = 200; /* 10ns */
343 if (spd.clk_cycle3 == 0xa0)
345 else if (spd.clk_cycle2 == 0xa0)
350 } else if (max_data_rate >= 323) { /* it is DDR 333 */
351 if (ddrc_clk <= 350 && ddrc_clk > 280) {
352 /* DDR controller clk at 280~350 */
353 effective_data_rate = 333; /* 6ns */
355 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
356 /* DDR controller clk at 230~280 */
357 effective_data_rate = 266; /* 7.5ns */
358 if (spd.clk_cycle2 == 0x75)
362 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
363 /* DDR controller clk at 90~230 */
364 effective_data_rate = 200; /* 10ns */
365 if (spd.clk_cycle3 == 0xa0)
367 else if (spd.clk_cycle2 == 0xa0)
372 } else if (max_data_rate >= 256) { /* it is DDR 266 */
373 if (ddrc_clk <= 350 && ddrc_clk > 280) {
374 /* DDR controller clk at 280~350 */
375 printf("DDR: DDR controller freq is more than "
376 "max data rate of the module\n");
378 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
379 /* DDR controller clk at 230~280 */
380 effective_data_rate = 266; /* 7.5ns */
382 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
383 /* DDR controller clk at 90~230 */
384 effective_data_rate = 200; /* 10ns */
385 if (spd.clk_cycle2 == 0xa0)
388 } else if (max_data_rate >= 190) { /* it is DDR 200 */
389 if (ddrc_clk <= 350 && ddrc_clk > 230) {
390 /* DDR controller clk at 230~350 */
391 printf("DDR: DDR controller freq is more than "
392 "max data rate of the module\n");
394 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
395 /* DDR controller clk at 90~230 */
396 effective_data_rate = 200; /* 10ns */
401 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
402 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
405 * Errata DDR6 work around: input enable 2 cycles earlier.
406 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
408 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
410 ddr->debug_reg = 0x201c0000; /* CL=2 */
411 else if (caslat == 3)
412 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
413 else if (caslat == 4)
414 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
416 __asm__ __volatile__ ("sync");
418 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
422 * Convert caslat clocks to DDR controller value.
423 * Force caslat_ctrl to be DDR Controller field-sized.
425 if (spd.mem_type == SPD_MEMTYPE_DDR) {
426 caslat_ctrl = (caslat + 1) & 0x07;
428 caslat_ctrl = (2 * caslat - 1) & 0x0f;
431 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
432 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
433 caslat, caslat_ctrl);
437 * Avoid writing for DDR I.
439 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
440 unsigned char taxpd_clk = 8; /* By the book. */
441 unsigned char tmrd_clk = 2; /* By the book. */
442 unsigned char act_pd_exit = 2; /* Empirical? */
443 unsigned char pre_pd_exit = 6; /* Empirical? */
445 ddr->timing_cfg_0 = (0
446 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
447 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
448 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
449 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
451 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
455 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
456 * use conservative value.
457 * For DDR II, they are bytes 36 and 37, in quarter nanos.
460 if (spd.mem_type == SPD_MEMTYPE_DDR) {
461 twr_clk = 3; /* Clocks */
462 twtr_clk = 1; /* Clocks */
464 twr_clk = picos_to_clk(spd.twr * 250);
465 twtr_clk = picos_to_clk(spd.twtr * 250);
469 * Calculate Trfc, in picos.
470 * DDR I: Byte 42 straight up in ns.
471 * DDR II: Byte 40 and 42 swizzled some, in ns.
473 if (spd.mem_type == SPD_MEMTYPE_DDR) {
474 trfc = spd.trfc * 1000; /* up to ps */
476 unsigned int byte40_table_ps[8] = {
487 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
488 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
490 trfc_clk = picos_to_clk(trfc);
493 * Trcd, Byte 29, from quarter nanos to ps and clocks.
495 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
498 * Convert trfc_clk to DDR controller fields. DDR I should
499 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
500 * 83xx controller has an extended REFREC field of three bits.
501 * The controller automatically adds 8 clocks to this value,
502 * so preadjust it down 8 first before splitting it up.
504 trfc_low = (trfc_clk - 8) & 0xf;
505 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
508 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
509 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
510 (trcd_clk << 20 ) | /* ACTTORW */
511 (caslat_ctrl << 16 ) | /* CASLAT */
512 (trfc_low << 12 ) | /* REFEC */
513 ((twr_clk & 0x07) << 8) | /* WRRREC */
514 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
515 ((twtr_clk & 0x07) << 0) /* WRTORD */
521 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
522 * which comes from Trcd, and also note that:
523 * add_lat + caslat must be >= 4
526 if (spd.mem_type == SPD_MEMTYPE_DDR2
527 && (odt_wr_cfg || odt_rd_cfg)
529 add_lat = trcd_clk - 1;
530 if ((add_lat + caslat) < 4) {
537 * Historically 0x2 == 4/8 clock delay.
538 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
545 * Minimum CKE Pulse Width.
546 * Four Activate Window
548 if (spd.mem_type == SPD_MEMTYPE_DDR) {
550 * This is a lie. It should really be 1, but if it is
551 * set to 1, bits overlap into the old controller's
552 * otherwise unused ACSM field. If we leave it 0, then
553 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
557 trtp_clk = 2; /* By the book. */
558 cke_min_clk = 1; /* By the book. */
559 four_act = 1; /* By the book. */
564 /* Convert SPD value from quarter nanos to picos. */
565 trtp_clk = picos_to_clk(spd.trtp * 250);
567 cke_min_clk = 3; /* By the book. */
568 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
572 * Empirically set ~MCAS-to-preamble override for DDR 2.
573 * Your milage will vary.
576 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
577 if (effective_data_rate == 266) {
578 cpo = 0x4; /* READ_LAT + 1/2 */
579 } else if (effective_data_rate == 333 || effective_data_rate == 400) {
580 cpo = 0x7; /* READ_LAT + 5/4 */
582 /* Automatic calibration */
587 ddr->timing_cfg_2 = (0
588 | ((add_lat & 0x7) << 28) /* ADD_LAT */
589 | ((cpo & 0x1f) << 23) /* CPO */
590 | ((wr_lat & 0x7) << 19) /* WR_LAT */
591 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
592 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
593 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
594 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
597 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
598 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
600 /* Check DIMM data bus width */
601 if (spd.dataw_lsb == 0x20) {
602 if (spd.mem_type == SPD_MEMTYPE_DDR)
603 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
605 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
606 debug("\n DDR DIMM: data bus width is 32 bit");
608 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
609 debug("\n DDR DIMM: data bus width is 64 bit");
612 /* Is this an ECC DDR chip? */
613 if (spd.config == 0x02)
614 debug(" with ECC\n");
616 debug(" without ECC\n");
618 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
619 Burst type is sequential
621 if (spd.mem_type == SPD_MEMTYPE_DDR) {
624 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
627 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
630 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
633 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
636 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
640 mode_odt_enable = 0x0; /* Default disabled */
641 if (odt_wr_cfg || odt_rd_cfg) {
643 * Bits 6 and 2 in Extended MRS(1)
644 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
645 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
647 mode_odt_enable = 0x40; /* 150 Ohm */
652 | (1 << (16 + 10)) /* DQS Differential disable */
653 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
654 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
655 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
656 | (caslat << 4) /* caslat */
657 | (burstlen << 0) /* Burst length */
660 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
663 * Clear EMRS2 and EMRS3.
665 ddr->sdram_mode2 = 0;
666 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
668 switch (spd.refresh) {
671 refresh_clk = picos_to_clk(15625000);
675 refresh_clk = picos_to_clk(3900000);
679 refresh_clk = picos_to_clk(7800000);
683 refresh_clk = picos_to_clk(31300000);
687 refresh_clk = picos_to_clk(62500000);
691 refresh_clk = picos_to_clk(125000000);
699 * Set BSTOPRE to 0x100 for page mode
700 * If auto-charge is used, set BSTOPRE = 0
702 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
703 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
709 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
710 if (odt_rd_cfg | odt_wr_cfg) {
711 odt_cfg = 0x2; /* ODT to IOs during reads */
714 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
716 | (0 << 26) /* True DQS */
717 | (odt_cfg << 21) /* ODT only read */
718 | (1 << 12) /* 1 refresh at a time */
721 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
724 #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
725 ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
727 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
734 * Figure out the settings for the sdram_cfg register. Build up
735 * the value in 'sdram_cfg' before writing since the write into
736 * the register will actually enable the memory controller, and all
737 * settings must be done before enabling.
739 * sdram_cfg[0] = 1 (ddr sdram logic enable)
740 * sdram_cfg[1] = 1 (self-refresh-enable)
741 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
744 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
745 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
747 if (spd.mem_type == SPD_MEMTYPE_DDR)
748 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
750 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
753 | SDRAM_CFG_MEM_EN /* DDR enable */
754 | SDRAM_CFG_SREN /* Self refresh */
755 | sdram_type /* SDRAM type */
758 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
759 if (spd.mod_attr & 0x02)
760 sdram_cfg |= SDRAM_CFG_RD_EN;
762 /* The DIMM is 32bit width */
763 if (spd.dataw_lsb == 0x20) {
764 if (spd.mem_type == SPD_MEMTYPE_DDR)
765 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
766 if (spd.mem_type == SPD_MEMTYPE_DDR2)
767 sdram_cfg |= SDRAM_CFG_32_BE;
772 #if defined(CONFIG_DDR_ECC)
773 /* Enable ECC with sdram_cfg[2] */
774 if (spd.config == 0x02) {
775 sdram_cfg |= 0x20000000;
777 /* disable error detection */
778 ddr->err_disable = ~ECC_ERROR_ENABLE;
779 /* set single bit error threshold to maximum value,
780 * reset counter to zero */
781 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
782 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
785 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
786 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
788 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
790 #if defined(CONFIG_DDR_2T_TIMING)
792 * Enable 2T timing by setting sdram_cfg[16].
794 sdram_cfg |= SDRAM_CFG_2T_EN;
796 /* Enable controller, and GO! */
797 ddr->sdram_cfg = sdram_cfg;
801 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
802 return memsize; /*in MBytes*/
804 #endif /* CONFIG_SPD_EEPROM */
806 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
808 * Use timebase counter, get_timer() is not availabe
809 * at this point of initialization yet.
811 static __inline__ unsigned long get_tbms (void)
814 unsigned long tbu1, tbu2;
816 unsigned long long tmp;
818 ulong tbclk = get_tbclk();
820 /* get the timebase ticks */
822 asm volatile ("mftbu %0":"=r" (tbu1):);
823 asm volatile ("mftb %0":"=r" (tbl):);
824 asm volatile ("mftbu %0":"=r" (tbu2):);
825 } while (tbu1 != tbu2);
827 /* convert ticks to ms */
828 tmp = (unsigned long long)(tbu1);
830 tmp += (unsigned long long)(tbl);
831 ms = tmp/(tbclk/1000);
837 * Initialize all of memory for ECC, then enable errors.
839 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
840 void ddr_enable_ecc(unsigned int dram_size)
842 volatile immap_t *immap = (immap_t *)CFG_IMMR;
843 volatile ddr83xx_t *ddr= &immap->ddr;
844 unsigned long t_start, t_end;
847 unsigned int pattern[2];
848 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
852 t_start = get_tbms();
853 pattern[0] = 0xdeadbeef;
854 pattern[1] = 0xdeadbeef;
856 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
857 debug("ddr init: CPU FP write method\n");
859 for (p = 0; p < (u64*)(size); p++) {
860 ppcDWstore((u32*)p, pattern);
862 __asm__ __volatile__ ("sync");
864 debug("ddr init: DMA method\n");
866 for (p = 0; p < (u64*)(size); p++) {
867 ppcDWstore((u32*)p, pattern);
869 __asm__ __volatile__ ("sync");
871 /* Initialise DMA for direct transfer */
873 /* Start DMA to transfer */
874 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
875 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
876 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
877 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
878 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
879 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
880 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
881 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
882 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
883 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
885 for (i = 1; i < dram_size / 0x800000; i++) {
886 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
893 debug("\nREADY!!\n");
894 debug("ddr init duration: %ld ms\n", t_end - t_start);
896 /* Clear All ECC Errors */
897 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
898 ddr->err_detect |= ECC_ERROR_DETECT_MME;
899 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
900 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
901 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
902 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
903 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
904 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
906 /* Disable ECC-Interrupts */
907 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
909 /* Enable errors for ECC */
910 ddr->err_disable &= ECC_ERROR_ENABLE;
912 __asm__ __volatile__ ("sync");
913 __asm__ __volatile__ ("isync");
915 #endif /* CONFIG_DDR_ECC */