cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26 #include <asm/io.h>
  27 #ifdef CONFIG_USB_EHCI_FSL
  28 #include <usb/ehci-fsl.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_QE
  34 extern qe_iop_conf_t qe_iop_conf_tab[];
  35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  36                          int open_drain, int assign);
  37 extern void qe_init(uint qe_base);
  38 extern void qe_reset(void);
  39
  40 static void config_qe_ioports(void)
  41 {
  42         u8      port, pin;
  43         int     dir, open_drain, assign;
  44         int     i;
  45
  46         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  47                 port            = qe_iop_conf_tab[i].port;
  48                 pin             = qe_iop_conf_tab[i].pin;
  49                 dir             = qe_iop_conf_tab[i].dir;
  50                 open_drain      = qe_iop_conf_tab[i].open_drain;
  51                 assign          = qe_iop_conf_tab[i].assign;
  52                 qe_config_iopin(port, pin, dir, open_drain, assign);
  53         }
  54 }
  55 #endif
  56
  57 /*
  58  * Breathe some life into the CPU...
  59  *
  60  * Set up the memory map,
  61  * initialize a bunch of registers,
  62  * initialize the UPM's
  63  */
  64 void cpu_init_f (volatile immap_t * im)
  65 {
  66         __be32 acr_mask =
  67 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  68                 (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  69 #endif
  70 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  71                 (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  72 #endif
  73                 0;
  74         __be32 acr_val =
  75 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  76                 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  77 #endif
  78 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  79                 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  80 #endif
  81                 0;
  82         __be32 spcr_mask =
  83 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  84                 (SPCR_OPT << SPCR_OPT_SHIFT) |
  85 #endif
  86 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  87                 (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
  88 #endif
  89 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  90                 (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
  91 #endif
  92 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  93                 (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
  94 #endif
  95                 0;
  96         __be32 spcr_val =
  97 #ifdef CONFIG_SYS_SPCR_OPT
  98                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
  99 #endif
 100 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
 101                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 102 #endif
 103 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 104                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 105 #endif
 106 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 107                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 108 #endif
 109                 0;
 110         __be32 sccr_mask =
 111 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 112                 (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 113 #endif
 114 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 115                 (SCCR_PCICM << SCCR_PCICM_SHIFT) |
 116 #endif
 117 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 118                 (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 119 #endif
 120 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 121                 (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 122 #endif
 123 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 124                 (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 125 #endif
 126 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 127                 (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 128 #endif
 129 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 130                 (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 131 #endif
 132 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 133                 (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 134 #endif
 135 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 136                 (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 137 #endif
 138 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 139                 (SCCR_SATACM << SCCR_SATACM_SHIFT) |
 140 #endif
 141                 0;
 142         __be32 sccr_val =
 143 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 144                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 145 #endif
 146 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 147                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 148 #endif
 149 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 150                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 151 #endif
 152 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 153                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 154 #endif
 155 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 156                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 157 #endif
 158 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 159                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 160 #endif
 161 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 162                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 163 #endif
 164 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 165                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 166 #endif
 167 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 168                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 169 #endif
 170 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 171                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 172 #endif
 173                 0;
 174         __be32 lcrr_mask =
 175 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 176                 LCRR_DBYP |
 177 #endif
 178 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 179                 LCRR_EADC |
 180 #endif
 181 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 182                 LCRR_CLKDIV |
 183 #endif
 184                 0;
 185         __be32 lcrr_val =
 186 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 187                 CONFIG_SYS_LCRR_DBYP |
 188 #endif
 189 #ifdef CONFIG_SYS_LCRR_EADC
 190                 CONFIG_SYS_LCRR_EADC |
 191 #endif
 192 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 193                 CONFIG_SYS_LCRR_CLKDIV |
 194 #endif
 195                 0;
 196
 197         /* Pointer is writable since we allocated a register for it */
 198         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 199
 200         /* Clear initial global data */
 201         memset ((void *) gd, 0, sizeof (gd_t));
 202
 203         /* system performance tweaking */
 204         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 205
 206         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 207
 208         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 209
 210         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 211         gd->reset_status = __raw_readl(&im->reset.rsr);
 212         __raw_writel(~(RSR_RES), &im->reset.rsr);
 213
 214         /* AER - Arbiter Event Register - store status */
 215         gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 216         gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 217
 218         /*
 219          * RMR - Reset Mode Register
 220          * contains checkstop reset enable (4.6.1.4)
 221          */
 222         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 223
 224         /* LCRR - Clock Ratio Register (10.3.1.16)
 225          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 226          */
 227         clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
 228         __raw_readl(&im->lbus.lcrr);
 229         isync();
 230
 231         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 232         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 233
 234         /* System General Purpose Register */
 235 #ifdef CONFIG_SYS_SICRH
 236 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 237         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 238         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 239                      &im->sysconf.sicrh);
 240 #else
 241         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 242 #endif
 243 #endif
 244 #ifdef CONFIG_SYS_SICRL
 245         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 246 #endif
 247 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 248         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 249 #endif
 250 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 251         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 252 #endif
 253
 254 #ifdef CONFIG_QE
 255         /* Config QE ioports */
 256         config_qe_ioports();
 257 #endif
 258
 259         /*
 260          * Memory Controller:
 261          */
 262
 263         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 264          * addresses - these have to be modified later when FLASH size
 265          * has been determined
 266          */
 267
 268 #if defined(CONFIG_SYS_BR0_PRELIM)  \
 269         && defined(CONFIG_SYS_OR0_PRELIM) \
 270         && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
 271         && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 272         im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
 273         im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
 274         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 275         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 276 #else
 277 #error  CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 278 #endif
 279
 280 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 281         im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
 282         im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
 283 #endif
 284 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 285         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 286         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 287 #endif
 288 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 289         im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
 290         im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
 291 #endif
 292 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 293         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 294         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 295 #endif
 296 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 297         im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
 298         im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
 299 #endif
 300 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 301         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 302         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 303 #endif
 304 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 305         im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
 306         im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
 307 #endif
 308 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 309         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 310         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 311 #endif
 312 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 313         im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
 314         im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
 315 #endif
 316 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 317         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 318         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 319 #endif
 320 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 321         im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
 322         im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
 323 #endif
 324 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 325         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 326         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 327 #endif
 328 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 329         im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
 330         im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
 331 #endif
 332 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 333         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 334         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 335 #endif
 336 #ifdef CONFIG_SYS_GPIO1_PRELIM
 337         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 338         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 339 #endif
 340 #ifdef CONFIG_SYS_GPIO2_PRELIM
 341         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 342         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 343 #endif
 344 #ifdef CONFIG_USB_EHCI_FSL
 345 #ifndef CONFIG_MPC834x
 346         uint32_t temp;
 347         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
 348
 349         /* Configure interface. */
 350         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 351
 352         /* Wait for clock to stabilize */
 353         do {
 354                 temp = __raw_readl(&ehci->control);
 355                 udelay(1000);
 356         } while (!(temp & PHY_CLK_VALID));
 357 #endif
 358 #endif
 359 }
 360
 361 int cpu_init_r (void)
 362 {
 363 #ifdef CONFIG_QE
 364         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 365
 366         qe_init(qe_base);
 367         qe_reset();
 368 #endif
 369         return 0;
 370 }
 371
 372 /*
 373  * Print out the bus arbiter event
 374  */
 375 #if defined(CONFIG_DISPLAY_AER_FULL)
 376 static int print_83xx_arb_event(int force)
 377 {
 378         static char* event[] = {
 379                 "Address Time Out",
 380                 "Data Time Out",
 381                 "Address Only Transfer Type",
 382                 "External Control Word Transfer Type",
 383                 "Reserved Transfer Type",
 384                 "Transfer Error",
 385                 "reserved",
 386                 "reserved"
 387         };
 388         static char* master[] = {
 389                 "e300 Core Data Transaction",
 390                 "reserved",
 391                 "e300 Core Instruction Fetch",
 392                 "reserved",
 393                 "TSEC1",
 394                 "TSEC2",
 395                 "USB MPH",
 396                 "USB DR",
 397                 "Encryption Core",
 398                 "I2C Boot Sequencer",
 399                 "JTAG",
 400                 "reserved",
 401                 "eSDHC",
 402                 "PCI1",
 403                 "PCI2",
 404                 "DMA",
 405                 "QUICC Engine 00",
 406                 "QUICC Engine 01",
 407                 "QUICC Engine 10",
 408                 "QUICC Engine 11",
 409                 "reserved",
 410                 "reserved",
 411                 "reserved",
 412                 "reserved",
 413                 "SATA1",
 414                 "SATA2",
 415                 "SATA3",
 416                 "SATA4",
 417                 "reserved",
 418                 "PCI Express 1",
 419                 "PCI Express 2",
 420                 "TDM-DMAC"
 421         };
 422         static char *transfer[] = {
 423                 "Address-only, Clean Block",
 424                 "Address-only, lwarx reservation set",
 425                 "Single-beat or Burst write",
 426                 "reserved",
 427                 "Address-only, Flush Block",
 428                 "reserved",
 429                 "Burst write",
 430                 "reserved",
 431                 "Address-only, sync",
 432                 "Address-only, tlbsync",
 433                 "Single-beat or Burst read",
 434                 "Single-beat or Burst read",
 435                 "Address-only, Kill Block",
 436                 "Address-only, icbi",
 437                 "Burst read",
 438                 "reserved",
 439                 "Address-only, eieio",
 440                 "reserved",
 441                 "Single-beat write",
 442                 "reserved",
 443                 "ecowx - Illegal single-beat write",
 444                 "reserved",
 445                 "reserved",
 446                 "reserved",
 447                 "Address-only, TLB Invalidate",
 448                 "reserved",
 449                 "Single-beat or Burst read",
 450                 "reserved",
 451                 "eciwx - Illegal single-beat read",
 452                 "reserved",
 453                 "Burst read",
 454                 "reserved"
 455         };
 456
 457         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 458                     >> AEATR_EVENT_SHIFT;
 459         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 460                       >> AEATR_MSTR_ID_SHIFT;
 461         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 462                    >> AEATR_TBST_SHIFT;
 463         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 464                     >> AEATR_TSIZE_SHIFT;
 465         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 466                     >> AEATR_TTYPE_SHIFT;
 467
 468         if (!force && !gd->arbiter_event_address)
 469                 return 0;
 470
 471         puts("Arbiter Event Status:\n");
 472         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 473         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 474         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 475         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 476                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 477         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 478
 479         return gd->arbiter_event_address;
 480 }
 481
 482 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 483
 484 static int print_83xx_arb_event(int force)
 485 {
 486         if (!force && !gd->arbiter_event_address)
 487                 return 0;
 488
 489         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 490                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 491
 492         return gd->arbiter_event_address;
 493 }
 494 #endif /* CONFIG_DISPLAY_AER_xxxx */
 495
 496 /*
 497  * Figure out the cause of the reset
 498  */
 499 int prt_83xx_rsr(void)
 500 {
 501         static struct {
 502                 ulong mask;
 503                 char *desc;
 504         } bits[] = {
 505                 {
 506                 RSR_SWSR, "Software Soft"}, {
 507                 RSR_SWHR, "Software Hard"}, {
 508                 RSR_JSRS, "JTAG Soft"}, {
 509                 RSR_CSHR, "Check Stop"}, {
 510                 RSR_SWRS, "Software Watchdog"}, {
 511                 RSR_BMRS, "Bus Monitor"}, {
 512                 RSR_SRS,  "External/Internal Soft"}, {
 513                 RSR_HRS,  "External/Internal Hard"}
 514         };
 515         static int n = sizeof bits / sizeof bits[0];
 516         ulong rsr = gd->reset_status;
 517         int i;
 518         char *sep;
 519
 520         puts("Reset Status:");
 521
 522         sep = " ";
 523         for (i = 0; i < n; i++)
 524                 if (rsr & bits[i].mask) {
 525                         printf("%s%s", sep, bits[i].desc);
 526                         sep = ", ";
 527                 }
 528         puts("\n");
 529
 530 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 531         print_83xx_arb_event(rsr & RSR_BMRS);
 532 #endif
 533         puts("\n");
 534
 535         return 0;
 536 }