2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * 20050101: Eran Liberty (liberty@freescale.com)
25 * Initial file creating (porting from 85XX & 8260)
32 DECLARE_GLOBAL_DATA_PTR;
35 extern qe_iop_conf_t qe_iop_conf_tab[];
36 extern void qe_config_iopin(u8 port, u8 pin, int dir,
37 int open_drain, int assign);
38 extern void qe_init(uint qe_base);
39 extern void qe_reset(void);
41 static void config_qe_ioports(void)
44 int dir, open_drain, assign;
47 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
48 port = qe_iop_conf_tab[i].port;
49 pin = qe_iop_conf_tab[i].pin;
50 dir = qe_iop_conf_tab[i].dir;
51 open_drain = qe_iop_conf_tab[i].open_drain;
52 assign = qe_iop_conf_tab[i].assign;
53 qe_config_iopin(port, pin, dir, open_drain, assign);
59 * Breathe some life into the CPU...
61 * Set up the memory map,
62 * initialize a bunch of registers,
63 * initialize the UPM's
65 void cpu_init_f (volatile immap_t * im)
67 /* Pointer is writable since we allocated a register for it */
68 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
70 /* Clear initial global data */
71 memset ((void *) gd, 0, sizeof (gd_t));
73 /* system performance tweaking */
75 #ifdef CFG_ACR_PIPE_DEP
76 /* Arbiter pipeline depth */
77 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
80 #ifdef CFG_SPCR_TSEC1EP
81 /* TSEC1 Emergency priority */
82 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
85 #ifdef CFG_SPCR_TSEC2EP
86 /* TSEC2 Emergency priority */
87 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
90 #ifdef CFG_SCCR_TSEC1CM
91 /* TSEC1 clock mode */
92 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
94 #ifdef CFG_SCCR_TSEC2CM
95 /* TSEC2 & I2C1 clock mode */
96 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
100 /* Arbiter repeat count */
101 im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
104 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
105 gd->reset_status = im->reset.rsr;
106 im->reset.rsr = ~(RSR_RES);
109 * RMR - Reset Mode Register
110 * contains checkstop reset enable (4.6.1.4)
112 im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
114 /* LCRR - Clock Ratio Register (10.3.1.16) */
115 im->lbus.lcrr = CFG_LCRR;
117 /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
118 im->sysconf.spcr |= SPCR_TBEN;
120 /* System General Purpose Register */
122 im->sysconf.sicrh = CFG_SICRH;
125 im->sysconf.sicrl = CFG_SICRL;
128 /* Config QE ioports */
136 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
137 * addresses - these have to be modified later when FLASH size
138 * has been determined
141 #if defined(CFG_BR0_PRELIM) \
142 && defined(CFG_OR0_PRELIM) \
143 && defined(CFG_LBLAWBAR0_PRELIM) \
144 && defined(CFG_LBLAWAR0_PRELIM)
145 im->lbus.bank[0].br = CFG_BR0_PRELIM;
146 im->lbus.bank[0].or = CFG_OR0_PRELIM;
147 im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
148 im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
150 #error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
153 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
154 im->lbus.bank[1].br = CFG_BR1_PRELIM;
155 im->lbus.bank[1].or = CFG_OR1_PRELIM;
157 #if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
158 im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
159 im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
161 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
162 im->lbus.bank[2].br = CFG_BR2_PRELIM;
163 im->lbus.bank[2].or = CFG_OR2_PRELIM;
165 #if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
166 im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
167 im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
169 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
170 im->lbus.bank[3].br = CFG_BR3_PRELIM;
171 im->lbus.bank[3].or = CFG_OR3_PRELIM;
173 #if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
174 im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
175 im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
177 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
178 im->lbus.bank[4].br = CFG_BR4_PRELIM;
179 im->lbus.bank[4].or = CFG_OR4_PRELIM;
181 #if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
182 im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
183 im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
185 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
186 im->lbus.bank[5].br = CFG_BR5_PRELIM;
187 im->lbus.bank[5].or = CFG_OR5_PRELIM;
189 #if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
190 im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
191 im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
193 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
194 im->lbus.bank[6].br = CFG_BR6_PRELIM;
195 im->lbus.bank[6].or = CFG_OR6_PRELIM;
197 #if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
198 im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
199 im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
201 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
202 im->lbus.bank[7].br = CFG_BR7_PRELIM;
203 im->lbus.bank[7].or = CFG_OR7_PRELIM;
205 #if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
206 im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
207 im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
209 #ifdef CFG_GPIO1_PRELIM
210 im->pgio[0].dir = CFG_GPIO1_DIR;
211 im->pgio[0].dat = CFG_GPIO1_DAT;
213 #ifdef CFG_GPIO2_PRELIM
214 im->pgio[1].dir = CFG_GPIO2_DIR;
215 im->pgio[1].dat = CFG_GPIO2_DAT;
219 int cpu_init_r (void)
222 uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */