2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
37 #if defined(CONFIG_OF_LIBFDT)
39 #include <libfdt_env.h>
42 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
53 immr = (immap_t *)CFG_IMMR;
55 if ((pvr & 0xFFFF0000) != PVR_83xx) {
56 puts("Not MPC83xx Family!!!\n");
60 spridr = immr->sysconf.spridr;
73 case SPR_8347E_REV10_TBGA:
74 case SPR_8347E_REV11_TBGA:
75 case SPR_8347E_REV31_TBGA:
76 case SPR_8347E_REV10_PBGA:
77 case SPR_8347E_REV11_PBGA:
78 case SPR_8347E_REV31_PBGA:
81 case SPR_8347_REV10_TBGA:
82 case SPR_8347_REV11_TBGA:
83 case SPR_8347_REV31_TBGA:
84 case SPR_8347_REV10_PBGA:
85 case SPR_8347_REV11_PBGA:
86 case SPR_8347_REV31_PBGA:
100 case SPR_8360E_REV11:
101 case SPR_8360E_REV12:
102 case SPR_8360E_REV20:
111 case SPR_8323E_REV10:
112 case SPR_8323E_REV11:
119 case SPR_8321E_REV10:
120 case SPR_8321E_REV11:
130 case SPR_8311E_REV10:
136 case SPR_8313E_REV10:
140 puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
144 #if defined(CONFIG_MPC834X)
145 /* Multiple revisons of 834x processors may have the same SPRIDR value.
146 * So use PVR to identify the revision number.
148 printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
150 printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
157 * Program a UPM with the code supplied in the table.
159 * The 'dummy' variable is used to increment the MAD. 'dummy' is
160 * supposed to be a pointer to the memory of the device being
161 * programmed by the UPM. The data in the MDR is written into
162 * memory and the MAD is incremented every time there's a read
163 * from 'dummy'. Unfortunately, the current prototype for this
164 * function doesn't allow for passing the address of this
165 * device, and changing the prototype will break a number lots
166 * of other code, so we need to use a round-about way of finding
167 * the value for 'dummy'.
169 * The value can be extracted from the base address bits of the
170 * Base Register (BR) associated with the specific UPM. To find
171 * that BR, we need to scan all 8 BRs until we find the one that
172 * has its MSEL bits matching the UPM we want. Once we know the
173 * right BR, we can extract the base address bits from it.
175 * The MxMR and the BR and OR of the chosen bank should all be
176 * configured before calling this function.
179 * upm: 0=UPMA, 1=UPMB, 2=UPMC
180 * table: Pointer to an array of values to program
181 * size: Number of elements in the array. Must be 64 or less.
183 void upmconfig (uint upm, uint *table, uint size)
185 #if defined(CONFIG_MPC834X)
186 volatile immap_t *immap = (immap_t *) CFG_IMMR;
187 volatile lbus83xx_t *lbus = &immap->lbus;
188 volatile uchar *dummy = NULL;
189 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
190 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
193 /* Scan all the banks to determine the base address of the device */
194 for (i = 0; i < 8; i++) {
195 if ((lbus->bank[i].br & BR_MSEL) == msel) {
196 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
202 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
206 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
207 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
209 for (i = 0; i < size; i++) {
210 lbus->mdr = table[i];
211 __asm__ __volatile__ ("sync");
212 *dummy; /* Write the value to memory and increment MAD */
213 __asm__ __volatile__ ("sync");
216 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
219 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
226 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
229 #ifndef MPC83xx_RESET
233 volatile immap_t *immap = (immap_t *) CFG_IMMR;
236 /* Interrupts and MMU off */
237 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
239 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
240 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
242 /* enable Reset Control Reg */
243 immap->reset.rpr = 0x52535445;
244 __asm__ __volatile__ ("sync");
245 __asm__ __volatile__ ("isync");
247 /* confirm Reset Control Reg is enabled */
248 while(!((immap->reset.rcer) & RCER_CRE));
250 printf("Resetting the board.");
255 /* perform reset, only one bit */
256 immap->reset.rcr = RCR_SWHR;
258 #else /* ! MPC83xx_RESET */
260 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
262 /* Interrupts and MMU off */
263 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
265 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
266 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
269 * Trying to execute the next instruction at a non-existing address
270 * should cause a machine check, resulting in reset
272 addr = CFG_RESET_ADDRESS;
274 printf("resetting the board.");
276 ((void (*)(void)) addr) ();
277 #endif /* MPC83xx_RESET */
284 * Get timebase clock frequency (like cpu_clk in Hz)
287 unsigned long get_tbclk(void)
291 tbclk = (gd->bus_clk + 3L) / 4L;
297 #if defined(CONFIG_WATCHDOG)
298 void watchdog_reset (void)
300 int re_enable = disable_interrupts();
302 /* Reset the 83xx watchdog */
303 volatile immap_t *immr = (immap_t *) CFG_IMMR;
304 immr->wdt.swsrr = 0x556c;
305 immr->wdt.swsrr = 0xaa39;
308 enable_interrupts ();
312 #if defined(CONFIG_OF_LIBFDT)
315 * "Setter" functions used to add/modify FDT entries.
317 static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd)
320 * Fix it up if it exists, don't create it if it doesn't exist.
322 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
323 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6);
325 return -FDT_ERR_NOTFOUND;
327 #ifdef CONFIG_HAS_ETH1
328 /* second onboard ethernet port */
329 static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd)
332 * Fix it up if it exists, don't create it if it doesn't exist.
334 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
335 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6);
337 return -FDT_ERR_NOTFOUND;
340 #ifdef CONFIG_HAS_ETH2
341 /* third onboard ethernet port */
342 static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd)
345 * Fix it up if it exists, don't create it if it doesn't exist.
347 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
348 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6);
350 return -FDT_ERR_NOTFOUND;
353 #ifdef CONFIG_HAS_ETH3
354 /* fourth onboard ethernet port */
355 static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd)
358 * Fix it up if it exists, don't create it if it doesn't exist.
360 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
361 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6);
363 return -FDT_ERR_NOTFOUND;
367 static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd)
371 * Create or update the property.
373 tmp = cpu_to_be32(bd->bi_busfreq);
374 return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
378 * Fixups to the fdt. If "create" is TRUE, the node is created
379 * unconditionally. If "create" is FALSE, the node is updated
380 * only if it already exists.
382 static const struct {
385 int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd);
395 { "/" OF_SOC "/serial@4500/",
399 { "/" OF_SOC "/serial@4600/",
403 #ifdef CONFIG_MPC83XX_TSEC1
404 { "/" OF_SOC "/ethernet@24000,
408 { "/" OF_SOC "/ethernet@24000,
413 #ifdef CONFIG_MPC83XX_TSEC2
414 { "/" OF_SOC "/ethernet@25000,
418 { "/" OF_SOC "/ethernet@25000,
423 #ifdef CONFIG_UEC_ETH1
424 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
425 { "/" OF_QE "/ucc@2000/mac-address",
429 { "/" OF_QE "/ucc@2000/mac-address",
433 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
434 { "/" OF_QE "/ucc@2200/mac-address",
438 { "/" OF_QE "/ucc@2200/mac-address",
444 #ifdef CONFIG_UEC_ETH2
445 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
446 { "/" OF_QE "/ucc@3000/mac-address",
450 { "/" OF_QE "/ucc@3000/mac-address",
454 #elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
455 { "/" OF_QE "/ucc@3200/mac-address",
459 { "/" OF_QE "/ucc@3200/mac-address",
468 ft_cpu_setup(void *blob, bd_t *bd)
474 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
475 nodeoffset = fdt_path_offset(fdt, fixup_props[j].node);
476 if (nodeoffset >= 0) {
477 err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd);
479 printf("set_fn/libfdt: %s %s returned %s\n",
488 #if defined(CONFIG_OF_FLAT_TREE)
490 ft_cpu_setup(void *blob, bd_t *bd)
496 clock = bd->bi_busfreq;
497 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
499 *p = cpu_to_be32(clock);
501 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
503 *p = cpu_to_be32(clock);
505 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
507 *p = cpu_to_be32(clock);
509 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
511 *p = cpu_to_be32(clock);
513 #ifdef CONFIG_MPC83XX_TSEC1
514 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
516 memcpy(p, bd->bi_enetaddr, 6);
518 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
520 memcpy(p, bd->bi_enetaddr, 6);
523 #ifdef CONFIG_MPC83XX_TSEC2
524 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
526 memcpy(p, bd->bi_enet1addr, 6);
528 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
530 memcpy(p, bd->bi_enet1addr, 6);
533 #ifdef CONFIG_UEC_ETH1
534 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
535 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
537 memcpy(p, bd->bi_enetaddr, 6);
539 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
541 memcpy(p, bd->bi_enetaddr, 6);
542 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
543 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
545 memcpy(p, bd->bi_enetaddr, 6);
547 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
549 memcpy(p, bd->bi_enetaddr, 6);
553 #ifdef CONFIG_UEC_ETH2
554 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
555 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
557 memcpy(p, bd->bi_enet1addr, 6);
559 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
561 memcpy(p, bd->bi_enet1addr, 6);
562 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
563 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
565 memcpy(p, bd->bi_enet1addr, 6);
567 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
569 memcpy(p, bd->bi_enet1addr, 6);
575 #if defined(CONFIG_DDR_ECC)
578 volatile immap_t *immap = (immap_t *)CFG_IMMR;
579 volatile dma83xx_t *dma = &immap->dma;
580 volatile u32 status = swab32(dma->dmasr0);
581 volatile u32 dmamr0 = swab32(dma->dmamr0);
585 /* initialize DMASARn, DMADAR and DMAABCRn */
586 dma->dmadar0 = (u32)0;
587 dma->dmasar0 = (u32)0;
590 __asm__ __volatile__ ("sync");
591 __asm__ __volatile__ ("isync");
594 dmamr0 &= ~DMA_CHANNEL_START;
595 dma->dmamr0 = swab32(dmamr0);
596 __asm__ __volatile__ ("sync");
597 __asm__ __volatile__ ("isync");
599 /* while the channel is busy, spin */
600 while(status & DMA_CHANNEL_BUSY) {
601 status = swab32(dma->dmasr0);
604 debug("DMA-init end\n");
609 volatile immap_t *immap = (immap_t *)CFG_IMMR;
610 volatile dma83xx_t *dma = &immap->dma;
611 volatile u32 status = swab32(dma->dmasr0);
612 volatile u32 byte_count = swab32(dma->dmabcr0);
614 /* while the channel is busy, spin */
615 while (status & DMA_CHANNEL_BUSY) {
616 status = swab32(dma->dmasr0);
619 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
620 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
626 int dma_xfer(void *dest, u32 count, void *src)
628 volatile immap_t *immap = (immap_t *)CFG_IMMR;
629 volatile dma83xx_t *dma = &immap->dma;
632 /* initialize DMASARn, DMADAR and DMAABCRn */
633 dma->dmadar0 = swab32((u32)dest);
634 dma->dmasar0 = swab32((u32)src);
635 dma->dmabcr0 = swab32(count);
637 __asm__ __volatile__ ("sync");
638 __asm__ __volatile__ ("isync");
640 /* init direct transfer, clear CS bit */
641 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
642 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
643 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
645 dma->dmamr0 = swab32(dmamr0);
647 __asm__ __volatile__ ("sync");
648 __asm__ __volatile__ ("isync");
650 /* set CS to start DMA transfer */
651 dmamr0 |= DMA_CHANNEL_START;
652 dma->dmamr0 = swab32(dmamr0);
653 __asm__ __volatile__ ("sync");
654 __asm__ __volatile__ ("isync");
656 return ((int)dma_check());
658 #endif /*CONFIG_DDR_ECC*/