2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
43 volatile immap_t *immr;
44 ulong clock = gd->cpu_clk;
50 const struct cpu_type {
53 } cpu_type_list [] = {
61 CPU_TYPE_ENTRY(8347_TBGA_),
62 CPU_TYPE_ENTRY(8347_PBGA_),
64 CPU_TYPE_ENTRY(8358_TBGA_),
65 CPU_TYPE_ENTRY(8358_PBGA_),
72 immr = (immap_t *)CONFIG_SYS_IMMR;
76 switch (pvr & 0xffff0000) {
94 printf("Unknown core, ");
97 spridr = immr->sysconf.spridr;
99 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
100 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
102 puts(cpu_type_list[i].name);
103 if (IS_E_PROCESSOR(spridr))
105 if (REVID_MAJOR(spridr) >= 2)
107 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
108 REVID_MINOR(spridr));
112 if (i == ARRAY_SIZE(cpu_type_list))
113 printf("(SPRIDR %08x unknown), ", spridr);
115 printf(" at %s MHz, ", strmhz(buf, clock));
117 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
124 * Program a UPM with the code supplied in the table.
126 * The 'dummy' variable is used to increment the MAD. 'dummy' is
127 * supposed to be a pointer to the memory of the device being
128 * programmed by the UPM. The data in the MDR is written into
129 * memory and the MAD is incremented every time there's a write
130 * to 'dummy'. Unfortunately, the current prototype for this
131 * function doesn't allow for passing the address of this
132 * device, and changing the prototype will break a number lots
133 * of other code, so we need to use a round-about way of finding
134 * the value for 'dummy'.
136 * The value can be extracted from the base address bits of the
137 * Base Register (BR) associated with the specific UPM. To find
138 * that BR, we need to scan all 8 BRs until we find the one that
139 * has its MSEL bits matching the UPM we want. Once we know the
140 * right BR, we can extract the base address bits from it.
142 * The MxMR and the BR and OR of the chosen bank should all be
143 * configured before calling this function.
146 * upm: 0=UPMA, 1=UPMB, 2=UPMC
147 * table: Pointer to an array of values to program
148 * size: Number of elements in the array. Must be 64 or less.
150 void upmconfig (uint upm, uint *table, uint size)
152 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
153 volatile fsl_lbus_t *lbus = &immap->lbus;
154 volatile uchar *dummy = NULL;
155 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
156 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
159 /* Scan all the banks to determine the base address of the device */
160 for (i = 0; i < 8; i++) {
161 if ((lbus->bank[i].br & BR_MSEL) == msel) {
162 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
168 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
172 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
173 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
175 for (i = 0; i < size; i++) {
176 lbus->mdr = table[i];
177 __asm__ __volatile__ ("sync");
178 *dummy = 0; /* Write the value to memory and increment MAD */
179 __asm__ __volatile__ ("sync");
180 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
183 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
189 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
192 #ifndef MPC83xx_RESET
196 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
199 /* Interrupts and MMU off */
200 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
202 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
203 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
205 /* enable Reset Control Reg */
206 immap->reset.rpr = 0x52535445;
207 __asm__ __volatile__ ("sync");
208 __asm__ __volatile__ ("isync");
210 /* confirm Reset Control Reg is enabled */
211 while(!((immap->reset.rcer) & RCER_CRE));
213 printf("Resetting the board.");
218 /* perform reset, only one bit */
219 immap->reset.rcr = RCR_SWHR;
221 #else /* ! MPC83xx_RESET */
223 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
225 /* Interrupts and MMU off */
226 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
228 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
229 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
232 * Trying to execute the next instruction at a non-existing address
233 * should cause a machine check, resulting in reset
235 addr = CONFIG_SYS_RESET_ADDRESS;
237 printf("resetting the board.");
239 ((void (*)(void)) addr) ();
240 #endif /* MPC83xx_RESET */
247 * Get timebase clock frequency (like cpu_clk in Hz)
250 unsigned long get_tbclk(void)
254 tbclk = (gd->bus_clk + 3L) / 4L;
260 #if defined(CONFIG_WATCHDOG)
261 void watchdog_reset (void)
263 int re_enable = disable_interrupts();
265 /* Reset the 83xx watchdog */
266 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
267 immr->wdt.swsrr = 0x556c;
268 immr->wdt.swsrr = 0xaa39;
271 enable_interrupts ();
275 #if defined(CONFIG_DDR_ECC)
278 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
279 volatile dma83xx_t *dma = &immap->dma;
280 volatile u32 status = swab32(dma->dmasr0);
281 volatile u32 dmamr0 = swab32(dma->dmamr0);
285 /* initialize DMASARn, DMADAR and DMAABCRn */
286 dma->dmadar0 = (u32)0;
287 dma->dmasar0 = (u32)0;
290 __asm__ __volatile__ ("sync");
291 __asm__ __volatile__ ("isync");
294 dmamr0 &= ~DMA_CHANNEL_START;
295 dma->dmamr0 = swab32(dmamr0);
296 __asm__ __volatile__ ("sync");
297 __asm__ __volatile__ ("isync");
299 /* while the channel is busy, spin */
300 while(status & DMA_CHANNEL_BUSY) {
301 status = swab32(dma->dmasr0);
304 debug("DMA-init end\n");
309 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
310 volatile dma83xx_t *dma = &immap->dma;
311 volatile u32 status = swab32(dma->dmasr0);
312 volatile u32 byte_count = swab32(dma->dmabcr0);
314 /* while the channel is busy, spin */
315 while (status & DMA_CHANNEL_BUSY) {
316 status = swab32(dma->dmasr0);
319 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
320 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
326 int dma_xfer(void *dest, u32 count, void *src)
328 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
329 volatile dma83xx_t *dma = &immap->dma;
332 /* initialize DMASARn, DMADAR and DMAABCRn */
333 dma->dmadar0 = swab32((u32)dest);
334 dma->dmasar0 = swab32((u32)src);
335 dma->dmabcr0 = swab32(count);
337 __asm__ __volatile__ ("sync");
338 __asm__ __volatile__ ("isync");
340 /* init direct transfer, clear CS bit */
341 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
342 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
343 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
345 dma->dmamr0 = swab32(dmamr0);
347 __asm__ __volatile__ ("sync");
348 __asm__ __volatile__ ("isync");
350 /* set CS to start DMA transfer */
351 dmamr0 |= DMA_CHANNEL_START;
352 dma->dmamr0 = swab32(dmamr0);
353 __asm__ __volatile__ ("sync");
354 __asm__ __volatile__ ("isync");
356 return ((int)dma_check());
358 #endif /*CONFIG_DDR_ECC*/
361 * Initializes on-chip ethernet controllers.
362 * to override, implement board_eth_init()
364 int cpu_eth_init(bd_t *bis)
366 #if defined(CONFIG_UEC_ETH1)
369 #if defined(CONFIG_UEC_ETH2)
372 #if defined(CONFIG_UEC_ETH3)
375 #if defined(CONFIG_UEC_ETH4)
378 #if defined(CONFIG_UEC_ETH5)
381 #if defined(CONFIG_UEC_ETH6)
384 #if defined(CONFIG_TSEC_ENET)
385 tsec_standard_init(bis);
391 * Initializes on-chip MMC controllers.
392 * to override, implement board_mmc_init()
394 int cpu_mmc_init(bd_t *bis)
396 #ifdef CONFIG_FSL_ESDHC
397 return fsl_esdhc_mmc_init(bis);