2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
34 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
41 volatile immap_t *immr;
42 ulong clock = gd->cpu_clk;
47 immr = (immap_t *)CFG_IMMR;
49 if ((pvr & 0xFFFF0000) != PVR_83xx) {
50 puts("Not MPC83xx Family!!!\n");
54 spridr = immr->sysconf.spridr;
67 case SPR_8347E_REV10_TBGA:
68 case SPR_8347E_REV11_TBGA:
69 case SPR_8347E_REV31_TBGA:
70 case SPR_8347E_REV10_PBGA:
71 case SPR_8347E_REV11_PBGA:
72 case SPR_8347E_REV31_PBGA:
75 case SPR_8347_REV10_TBGA:
76 case SPR_8347_REV11_TBGA:
77 case SPR_8347_REV31_TBGA:
78 case SPR_8347_REV10_PBGA:
79 case SPR_8347_REV11_PBGA:
80 case SPR_8347_REV31_PBGA:
103 case SPR_8323E_REV10:
104 case SPR_8323E_REV11:
111 case SPR_8321E_REV10:
112 case SPR_8321E_REV11:
120 puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
124 #if defined(CONFIG_MPC834X)
125 /* Multiple revisons of 834x processors may have the same SPRIDR value.
126 * So use PVR to identify the revision number.
128 printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
130 printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
137 * Program a UPM with the code supplied in the table.
139 * The 'dummy' variable is used to increment the MAD. 'dummy' is
140 * supposed to be a pointer to the memory of the device being
141 * programmed by the UPM. The data in the MDR is written into
142 * memory and the MAD is incremented every time there's a read
143 * from 'dummy'. Unfortunately, the current prototype for this
144 * function doesn't allow for passing the address of this
145 * device, and changing the prototype will break a number lots
146 * of other code, so we need to use a round-about way of finding
147 * the value for 'dummy'.
149 * The value can be extracted from the base address bits of the
150 * Base Register (BR) associated with the specific UPM. To find
151 * that BR, we need to scan all 8 BRs until we find the one that
152 * has its MSEL bits matching the UPM we want. Once we know the
153 * right BR, we can extract the base address bits from it.
155 * The MxMR and the BR and OR of the chosen bank should all be
156 * configured before calling this function.
159 * upm: 0=UPMA, 1=UPMB, 2=UPMC
160 * table: Pointer to an array of values to program
161 * size: Number of elements in the array. Must be 64 or less.
163 void upmconfig (uint upm, uint *table, uint size)
165 #if defined(CONFIG_MPC834X)
166 volatile immap_t *immap = (immap_t *) CFG_IMMR;
167 volatile lbus83xx_t *lbus = &immap->lbus;
168 volatile uchar *dummy = NULL;
169 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
170 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
173 /* Scan all the banks to determine the base address of the device */
174 for (i = 0; i < 8; i++) {
175 if ((lbus->bank[i].br & BR_MSEL) == msel) {
176 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
182 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
186 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
187 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
189 for (i = 0; i < size; i++) {
190 lbus->mdr = table[i];
191 __asm__ __volatile__ ("sync");
192 *dummy; /* Write the value to memory and increment MAD */
193 __asm__ __volatile__ ("sync");
196 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
199 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
206 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
209 #ifndef MPC83xx_RESET
213 volatile immap_t *immap = (immap_t *) CFG_IMMR;
216 /* Interrupts and MMU off */
217 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
219 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
220 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
222 /* enable Reset Control Reg */
223 immap->reset.rpr = 0x52535445;
224 __asm__ __volatile__ ("sync");
225 __asm__ __volatile__ ("isync");
227 /* confirm Reset Control Reg is enabled */
228 while(!((immap->reset.rcer) & RCER_CRE));
230 printf("Resetting the board.");
235 /* perform reset, only one bit */
236 immap->reset.rcr = RCR_SWHR;
238 #else /* ! MPC83xx_RESET */
240 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
242 /* Interrupts and MMU off */
243 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
245 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
246 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
249 * Trying to execute the next instruction at a non-existing address
250 * should cause a machine check, resulting in reset
252 addr = CFG_RESET_ADDRESS;
254 printf("resetting the board.");
256 ((void (*)(void)) addr) ();
257 #endif /* MPC83xx_RESET */
264 * Get timebase clock frequency (like cpu_clk in Hz)
267 unsigned long get_tbclk(void)
271 tbclk = (gd->bus_clk + 3L) / 4L;
277 #if defined(CONFIG_WATCHDOG)
278 void watchdog_reset (void)
280 int re_enable = disable_interrupts();
282 /* Reset the 83xx watchdog */
283 volatile immap_t *immr = (immap_t *) CFG_IMMR;
284 immr->wdt.swsrr = 0x556c;
285 immr->wdt.swsrr = 0xaa39;
288 enable_interrupts ();
292 #if defined(CONFIG_OF_FLAT_TREE)
294 ft_cpu_setup(void *blob, bd_t *bd)
300 clock = bd->bi_busfreq;
301 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
303 *p = cpu_to_be32(clock);
305 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
307 *p = cpu_to_be32(clock);
309 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
311 *p = cpu_to_be32(clock);
313 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
315 *p = cpu_to_be32(clock);
317 #ifdef CONFIG_MPC83XX_TSEC1
318 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
320 memcpy(p, bd->bi_enetaddr, 6);
323 #ifdef CONFIG_MPC83XX_TSEC2
324 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
326 memcpy(p, bd->bi_enet1addr, 6);
331 #if defined(CONFIG_DDR_ECC)
334 volatile immap_t *immap = (immap_t *)CFG_IMMR;
335 volatile dma83xx_t *dma = &immap->dma;
336 volatile u32 status = swab32(dma->dmasr0);
337 volatile u32 dmamr0 = swab32(dma->dmamr0);
341 /* initialize DMASARn, DMADAR and DMAABCRn */
342 dma->dmadar0 = (u32)0;
343 dma->dmasar0 = (u32)0;
346 __asm__ __volatile__ ("sync");
347 __asm__ __volatile__ ("isync");
350 dmamr0 &= ~DMA_CHANNEL_START;
351 dma->dmamr0 = swab32(dmamr0);
352 __asm__ __volatile__ ("sync");
353 __asm__ __volatile__ ("isync");
355 /* while the channel is busy, spin */
356 while(status & DMA_CHANNEL_BUSY) {
357 status = swab32(dma->dmasr0);
360 debug("DMA-init end\n");
365 volatile immap_t *immap = (immap_t *)CFG_IMMR;
366 volatile dma83xx_t *dma = &immap->dma;
367 volatile u32 status = swab32(dma->dmasr0);
368 volatile u32 byte_count = swab32(dma->dmabcr0);
370 /* while the channel is busy, spin */
371 while (status & DMA_CHANNEL_BUSY) {
372 status = swab32(dma->dmasr0);
375 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
376 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
382 int dma_xfer(void *dest, u32 count, void *src)
384 volatile immap_t *immap = (immap_t *)CFG_IMMR;
385 volatile dma83xx_t *dma = &immap->dma;
388 /* initialize DMASARn, DMADAR and DMAABCRn */
389 dma->dmadar0 = swab32((u32)dest);
390 dma->dmasar0 = swab32((u32)src);
391 dma->dmabcr0 = swab32(count);
393 __asm__ __volatile__ ("sync");
394 __asm__ __volatile__ ("isync");
396 /* init direct transfer, clear CS bit */
397 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
398 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
399 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
401 dma->dmamr0 = swab32(dmamr0);
403 __asm__ __volatile__ ("sync");
404 __asm__ __volatile__ ("isync");
406 /* set CS to start DMA transfer */
407 dmamr0 |= DMA_CHANNEL_START;
408 dma->dmamr0 = swab32(dmamr0);
409 __asm__ __volatile__ ("sync");
410 __asm__ __volatile__ ("isync");
412 return ((int)dma_check());
414 #endif /*CONFIG_DDR_ECC*/