2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
34 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
41 volatile immap_t *immr;
42 ulong clock = gd->cpu_clk;
47 immr = (immap_t *)CFG_IMMR;
49 if ((pvr & 0xFFFF0000) != PVR_83xx) {
50 puts("Not MPC83xx Family!!!\n");
54 spridr = immr->sysconf.spridr;
65 case SPR_8347E_REV10_TBGA:
66 case SPR_8347E_REV11_TBGA:
67 case SPR_8347E_REV10_PBGA:
68 case SPR_8347E_REV11_PBGA:
71 case SPR_8347_REV10_TBGA:
72 case SPR_8347_REV11_TBGA:
73 case SPR_8347_REV10_PBGA:
74 case SPR_8347_REV11_PBGA:
96 puts("Rev: Unknown\n");
97 return -1; /* Not sure what this is */
100 #if defined(CONFIG_MPC8349)
101 printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
103 printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
110 * Program a UPM with the code supplied in the table.
112 * The 'dummy' variable is used to increment the MAD. 'dummy' is
113 * supposed to be a pointer to the memory of the device being
114 * programmed by the UPM. The data in the MDR is written into
115 * memory and the MAD is incremented every time there's a read
116 * from 'dummy'. Unfortunately, the current prototype for this
117 * function doesn't allow for passing the address of this
118 * device, and changing the prototype will break a number lots
119 * of other code, so we need to use a round-about way of finding
120 * the value for 'dummy'.
122 * The value can be extracted from the base address bits of the
123 * Base Register (BR) associated with the specific UPM. To find
124 * that BR, we need to scan all 8 BRs until we find the one that
125 * has its MSEL bits matching the UPM we want. Once we know the
126 * right BR, we can extract the base address bits from it.
128 * The MxMR and the BR and OR of the chosen bank should all be
129 * configured before calling this function.
132 * upm: 0=UPMA, 1=UPMB, 2=UPMC
133 * table: Pointer to an array of values to program
134 * size: Number of elements in the array. Must be 64 or less.
136 void upmconfig (uint upm, uint *table, uint size)
138 #if defined(CONFIG_MPC834X)
139 volatile immap_t *immap = (immap_t *) CFG_IMMR;
140 volatile lbus83xx_t *lbus = &immap->lbus;
141 volatile uchar *dummy = NULL;
142 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
143 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
146 /* Scan all the banks to determine the base address of the device */
147 for (i = 0; i < 8; i++) {
148 if ((lbus->bank[i].br & BR_MSEL) == msel) {
149 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
155 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
159 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
160 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
162 for (i = 0; i < size; i++) {
163 lbus->mdr = table[i];
164 __asm__ __volatile__ ("sync");
165 *dummy; /* Write the value to memory and increment MAD */
166 __asm__ __volatile__ ("sync");
169 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
172 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
179 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
182 #ifndef MPC83xx_RESET
186 volatile immap_t *immap = (immap_t *) CFG_IMMR;
189 /* Interrupts and MMU off */
190 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
192 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
193 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
195 /* enable Reset Control Reg */
196 immap->reset.rpr = 0x52535445;
197 __asm__ __volatile__ ("sync");
198 __asm__ __volatile__ ("isync");
200 /* confirm Reset Control Reg is enabled */
201 while(!((immap->reset.rcer) & RCER_CRE));
203 printf("Resetting the board.");
208 /* perform reset, only one bit */
209 immap->reset.rcr = RCR_SWHR;
211 #else /* ! MPC83xx_RESET */
213 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
215 /* Interrupts and MMU off */
216 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
218 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
219 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
222 * Trying to execute the next instruction at a non-existing address
223 * should cause a machine check, resulting in reset
225 addr = CFG_RESET_ADDRESS;
227 printf("resetting the board.");
229 ((void (*)(void)) addr) ();
230 #endif /* MPC83xx_RESET */
237 * Get timebase clock frequency (like cpu_clk in Hz)
240 unsigned long get_tbclk(void)
244 tbclk = (gd->bus_clk + 3L) / 4L;
250 #if defined(CONFIG_WATCHDOG)
251 void watchdog_reset (void)
253 #ifdef CONFIG_MPC834X
254 int re_enable = disable_interrupts();
256 /* Reset the 83xx watchdog */
257 volatile immap_t *immr = (immap_t *) CFG_IMMR;
258 immr->wdt.swsrr = 0x556c;
259 immr->wdt.swsrr = 0xaa39;
262 enable_interrupts ();
269 #if defined(CONFIG_OF_FLAT_TREE)
271 ft_cpu_setup(void *blob, bd_t *bd)
277 clock = bd->bi_busfreq;
278 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
280 *p = cpu_to_be32(clock);
282 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
284 *p = cpu_to_be32(clock);
286 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
288 *p = cpu_to_be32(clock);
290 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
292 *p = cpu_to_be32(clock);
294 #ifdef CONFIG_MPC83XX_TSEC1
295 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
296 memcpy(p, bd->bi_enetaddr, 6);
299 #ifdef CONFIG_MPC83XX_TSEC2
300 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
301 memcpy(p, bd->bi_enet1addr, 6);
306 #if defined(CONFIG_DDR_ECC)
309 volatile immap_t *immap = (immap_t *)CFG_IMMR;
310 volatile dma83xx_t *dma = &immap->dma;
311 volatile u32 status = swab32(dma->dmasr0);
312 volatile u32 dmamr0 = swab32(dma->dmamr0);
316 /* initialize DMASARn, DMADAR and DMAABCRn */
317 dma->dmadar0 = (u32)0;
318 dma->dmasar0 = (u32)0;
321 __asm__ __volatile__ ("sync");
322 __asm__ __volatile__ ("isync");
325 dmamr0 &= ~DMA_CHANNEL_START;
326 dma->dmamr0 = swab32(dmamr0);
327 __asm__ __volatile__ ("sync");
328 __asm__ __volatile__ ("isync");
330 /* while the channel is busy, spin */
331 while(status & DMA_CHANNEL_BUSY) {
332 status = swab32(dma->dmasr0);
335 debug("DMA-init end\n");
340 volatile immap_t *immap = (immap_t *)CFG_IMMR;
341 volatile dma83xx_t *dma = &immap->dma;
342 volatile u32 status = swab32(dma->dmasr0);
343 volatile u32 byte_count = swab32(dma->dmabcr0);
345 /* while the channel is busy, spin */
346 while (status & DMA_CHANNEL_BUSY) {
347 status = swab32(dma->dmasr0);
350 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
351 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
357 int dma_xfer(void *dest, u32 count, void *src)
359 volatile immap_t *immap = (immap_t *)CFG_IMMR;
360 volatile dma83xx_t *dma = &immap->dma;
363 /* initialize DMASARn, DMADAR and DMAABCRn */
364 dma->dmadar0 = swab32((u32)dest);
365 dma->dmasar0 = swab32((u32)src);
366 dma->dmabcr0 = swab32(count);
368 __asm__ __volatile__ ("sync");
369 __asm__ __volatile__ ("isync");
371 /* init direct transfer, clear CS bit */
372 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
373 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
374 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
376 dma->dmamr0 = swab32(dmamr0);
378 __asm__ __volatile__ ("sync");
379 __asm__ __volatile__ ("isync");
381 /* set CS to start DMA transfer */
382 dmamr0 |= DMA_CHANNEL_START;
383 dma->dmamr0 = swab32(dmamr0);
384 __asm__ __volatile__ ("sync");
385 __asm__ __volatile__ ("isync");
387 return ((int)dma_check());
389 #endif /*CONFIG_DDR_ECC*/