2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
37 #if defined(CONFIG_OF_LIBFDT)
39 #include <libfdt_env.h>
42 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
53 immr = (immap_t *)CFG_IMMR;
57 switch (pvr & 0xffff0000) {
71 printf("Unknown core, ");
74 spridr = immr->sysconf.spridr;
86 case SPR_8347E_REV10_TBGA:
87 case SPR_8347E_REV11_TBGA:
88 case SPR_8347E_REV31_TBGA:
89 case SPR_8347E_REV10_PBGA:
90 case SPR_8347E_REV11_PBGA:
91 case SPR_8347E_REV31_PBGA:
94 case SPR_8347_REV10_TBGA:
95 case SPR_8347_REV11_TBGA:
96 case SPR_8347_REV31_TBGA:
97 case SPR_8347_REV10_PBGA:
98 case SPR_8347_REV11_PBGA:
99 case SPR_8347_REV31_PBGA:
102 case SPR_8343E_REV10:
103 case SPR_8343E_REV11:
104 case SPR_8343E_REV31:
112 case SPR_8360E_REV10:
113 case SPR_8360E_REV11:
114 case SPR_8360E_REV12:
115 case SPR_8360E_REV20:
116 case SPR_8360E_REV21:
126 case SPR_8323E_REV10:
127 case SPR_8323E_REV11:
134 case SPR_8321E_REV10:
135 case SPR_8321E_REV11:
145 case SPR_8311E_REV10:
151 case SPR_8313E_REV10:
155 printf("Rev: Unknown revision number:%08x\n"
156 "Warning: Unsupported cpu revision!\n",spridr);
160 #if defined(CONFIG_MPC834X)
161 /* Multiple revisons of 834x processors may have the same SPRIDR value.
162 * So use PVR to identify the revision number.
164 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
166 printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
168 printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
175 * Program a UPM with the code supplied in the table.
177 * The 'dummy' variable is used to increment the MAD. 'dummy' is
178 * supposed to be a pointer to the memory of the device being
179 * programmed by the UPM. The data in the MDR is written into
180 * memory and the MAD is incremented every time there's a read
181 * from 'dummy'. Unfortunately, the current prototype for this
182 * function doesn't allow for passing the address of this
183 * device, and changing the prototype will break a number lots
184 * of other code, so we need to use a round-about way of finding
185 * the value for 'dummy'.
187 * The value can be extracted from the base address bits of the
188 * Base Register (BR) associated with the specific UPM. To find
189 * that BR, we need to scan all 8 BRs until we find the one that
190 * has its MSEL bits matching the UPM we want. Once we know the
191 * right BR, we can extract the base address bits from it.
193 * The MxMR and the BR and OR of the chosen bank should all be
194 * configured before calling this function.
197 * upm: 0=UPMA, 1=UPMB, 2=UPMC
198 * table: Pointer to an array of values to program
199 * size: Number of elements in the array. Must be 64 or less.
201 void upmconfig (uint upm, uint *table, uint size)
203 #if defined(CONFIG_MPC834X)
204 volatile immap_t *immap = (immap_t *) CFG_IMMR;
205 volatile lbus83xx_t *lbus = &immap->lbus;
206 volatile uchar *dummy = NULL;
207 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
208 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
211 /* Scan all the banks to determine the base address of the device */
212 for (i = 0; i < 8; i++) {
213 if ((lbus->bank[i].br & BR_MSEL) == msel) {
214 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
220 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
224 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
225 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
227 for (i = 0; i < size; i++) {
228 lbus->mdr = table[i];
229 __asm__ __volatile__ ("sync");
230 *dummy; /* Write the value to memory and increment MAD */
231 __asm__ __volatile__ ("sync");
234 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
237 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
244 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
247 #ifndef MPC83xx_RESET
251 volatile immap_t *immap = (immap_t *) CFG_IMMR;
254 /* Interrupts and MMU off */
255 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
257 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
258 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
260 /* enable Reset Control Reg */
261 immap->reset.rpr = 0x52535445;
262 __asm__ __volatile__ ("sync");
263 __asm__ __volatile__ ("isync");
265 /* confirm Reset Control Reg is enabled */
266 while(!((immap->reset.rcer) & RCER_CRE));
268 printf("Resetting the board.");
273 /* perform reset, only one bit */
274 immap->reset.rcr = RCR_SWHR;
276 #else /* ! MPC83xx_RESET */
278 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
280 /* Interrupts and MMU off */
281 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
283 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
284 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
287 * Trying to execute the next instruction at a non-existing address
288 * should cause a machine check, resulting in reset
290 addr = CFG_RESET_ADDRESS;
292 printf("resetting the board.");
294 ((void (*)(void)) addr) ();
295 #endif /* MPC83xx_RESET */
302 * Get timebase clock frequency (like cpu_clk in Hz)
305 unsigned long get_tbclk(void)
309 tbclk = (gd->bus_clk + 3L) / 4L;
315 #if defined(CONFIG_WATCHDOG)
316 void watchdog_reset (void)
318 int re_enable = disable_interrupts();
320 /* Reset the 83xx watchdog */
321 volatile immap_t *immr = (immap_t *) CFG_IMMR;
322 immr->wdt.swsrr = 0x556c;
323 immr->wdt.swsrr = 0xaa39;
326 enable_interrupts ();
330 #if defined(CONFIG_OF_LIBFDT)
333 * "Setter" functions used to add/modify FDT entries.
335 static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd)
338 * Fix it up if it exists, don't create it if it doesn't exist.
340 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
341 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6);
343 return -FDT_ERR_NOTFOUND;
345 #ifdef CONFIG_HAS_ETH1
346 /* second onboard ethernet port */
347 static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd)
350 * Fix it up if it exists, don't create it if it doesn't exist.
352 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
353 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6);
355 return -FDT_ERR_NOTFOUND;
358 #ifdef CONFIG_HAS_ETH2
359 /* third onboard ethernet port */
360 static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd)
363 * Fix it up if it exists, don't create it if it doesn't exist.
365 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
366 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6);
368 return -FDT_ERR_NOTFOUND;
371 #ifdef CONFIG_HAS_ETH3
372 /* fourth onboard ethernet port */
373 static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd)
376 * Fix it up if it exists, don't create it if it doesn't exist.
378 if (fdt_get_property(fdt, nodeoffset, name, 0)) {
379 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6);
381 return -FDT_ERR_NOTFOUND;
385 static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd)
389 * Create or update the property.
391 tmp = cpu_to_be32(bd->bi_busfreq);
392 return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
396 * Fixups to the fdt. If "create" is TRUE, the node is created
397 * unconditionally. If "create" is FALSE, the node is updated
398 * only if it already exists.
400 static const struct {
403 int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd);
413 { "/" OF_SOC "/serial@4500/",
417 { "/" OF_SOC "/serial@4600/",
422 { "/" OF_SOC "/ethernet@24000,
426 { "/" OF_SOC "/ethernet@24000,
432 { "/" OF_SOC "/ethernet@25000,
436 { "/" OF_SOC "/ethernet@25000,
441 #ifdef CONFIG_UEC_ETH1
442 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
443 { "/" OF_QE "/ucc@2000/mac-address",
447 { "/" OF_QE "/ucc@2000/mac-address",
451 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
452 { "/" OF_QE "/ucc@2200/mac-address",
456 { "/" OF_QE "/ucc@2200/mac-address",
462 #ifdef CONFIG_UEC_ETH2
463 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
464 { "/" OF_QE "/ucc@3000/mac-address",
468 { "/" OF_QE "/ucc@3000/mac-address",
472 #elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
473 { "/" OF_QE "/ucc@3200/mac-address",
477 { "/" OF_QE "/ucc@3200/mac-address",
486 ft_cpu_setup(void *blob, bd_t *bd)
492 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
493 nodeoffset = fdt_path_offset(fdt, fixup_props[j].node);
494 if (nodeoffset >= 0) {
495 err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd);
497 printf("set_fn/libfdt: %s %s returned %s\n",
506 #if defined(CONFIG_OF_FLAT_TREE)
508 ft_cpu_setup(void *blob, bd_t *bd)
514 clock = bd->bi_busfreq;
515 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
517 *p = cpu_to_be32(clock);
519 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
521 *p = cpu_to_be32(clock);
523 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
525 *p = cpu_to_be32(clock);
527 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
529 *p = cpu_to_be32(clock);
532 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
534 memcpy(p, bd->bi_enetaddr, 6);
536 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
538 memcpy(p, bd->bi_enetaddr, 6);
542 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
544 memcpy(p, bd->bi_enet1addr, 6);
546 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
548 memcpy(p, bd->bi_enet1addr, 6);
551 #ifdef CONFIG_UEC_ETH1
552 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
553 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
555 memcpy(p, bd->bi_enetaddr, 6);
557 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
559 memcpy(p, bd->bi_enetaddr, 6);
560 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
561 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
563 memcpy(p, bd->bi_enetaddr, 6);
565 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
567 memcpy(p, bd->bi_enetaddr, 6);
571 #ifdef CONFIG_UEC_ETH2
572 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
573 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
575 memcpy(p, bd->bi_enet1addr, 6);
577 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
579 memcpy(p, bd->bi_enet1addr, 6);
580 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
581 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
583 memcpy(p, bd->bi_enet1addr, 6);
585 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
587 memcpy(p, bd->bi_enet1addr, 6);
593 #if defined(CONFIG_DDR_ECC)
596 volatile immap_t *immap = (immap_t *)CFG_IMMR;
597 volatile dma83xx_t *dma = &immap->dma;
598 volatile u32 status = swab32(dma->dmasr0);
599 volatile u32 dmamr0 = swab32(dma->dmamr0);
603 /* initialize DMASARn, DMADAR and DMAABCRn */
604 dma->dmadar0 = (u32)0;
605 dma->dmasar0 = (u32)0;
608 __asm__ __volatile__ ("sync");
609 __asm__ __volatile__ ("isync");
612 dmamr0 &= ~DMA_CHANNEL_START;
613 dma->dmamr0 = swab32(dmamr0);
614 __asm__ __volatile__ ("sync");
615 __asm__ __volatile__ ("isync");
617 /* while the channel is busy, spin */
618 while(status & DMA_CHANNEL_BUSY) {
619 status = swab32(dma->dmasr0);
622 debug("DMA-init end\n");
627 volatile immap_t *immap = (immap_t *)CFG_IMMR;
628 volatile dma83xx_t *dma = &immap->dma;
629 volatile u32 status = swab32(dma->dmasr0);
630 volatile u32 byte_count = swab32(dma->dmabcr0);
632 /* while the channel is busy, spin */
633 while (status & DMA_CHANNEL_BUSY) {
634 status = swab32(dma->dmasr0);
637 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
638 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
644 int dma_xfer(void *dest, u32 count, void *src)
646 volatile immap_t *immap = (immap_t *)CFG_IMMR;
647 volatile dma83xx_t *dma = &immap->dma;
650 /* initialize DMASARn, DMADAR and DMAABCRn */
651 dma->dmadar0 = swab32((u32)dest);
652 dma->dmasar0 = swab32((u32)src);
653 dma->dmabcr0 = swab32(count);
655 __asm__ __volatile__ ("sync");
656 __asm__ __volatile__ ("isync");
658 /* init direct transfer, clear CS bit */
659 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
660 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
661 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
663 dma->dmamr0 = swab32(dmamr0);
665 __asm__ __volatile__ ("sync");
666 __asm__ __volatile__ ("isync");
668 /* set CS to start DMA transfer */
669 dmamr0 |= DMA_CHANNEL_START;
670 dma->dmamr0 = swab32(dmamr0);
671 __asm__ __volatile__ ("sync");
672 __asm__ __volatile__ ("isync");
674 return ((int)dma_check());
676 #endif /*CONFIG_DDR_ECC*/