2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
37 #if defined(CONFIG_OF_LIBFDT)
39 #include <libfdt_env.h>
42 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
53 immr = (immap_t *)CFG_IMMR;
55 if ((pvr & 0xFFFF0000) != PVR_83xx) {
56 puts("Not MPC83xx Family!!!\n");
60 spridr = immr->sysconf.spridr;
73 case SPR_8347E_REV10_TBGA:
74 case SPR_8347E_REV11_TBGA:
75 case SPR_8347E_REV31_TBGA:
76 case SPR_8347E_REV10_PBGA:
77 case SPR_8347E_REV11_PBGA:
78 case SPR_8347E_REV31_PBGA:
81 case SPR_8347_REV10_TBGA:
82 case SPR_8347_REV11_TBGA:
83 case SPR_8347_REV31_TBGA:
84 case SPR_8347_REV10_PBGA:
85 case SPR_8347_REV11_PBGA:
86 case SPR_8347_REV31_PBGA:
100 case SPR_8360E_REV11:
101 case SPR_8360E_REV12:
102 case SPR_8360E_REV20:
111 case SPR_8323E_REV10:
112 case SPR_8323E_REV11:
119 case SPR_8321E_REV10:
120 case SPR_8321E_REV11:
128 puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
132 #if defined(CONFIG_MPC834X)
133 /* Multiple revisons of 834x processors may have the same SPRIDR value.
134 * So use PVR to identify the revision number.
136 printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
138 printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
145 * Program a UPM with the code supplied in the table.
147 * The 'dummy' variable is used to increment the MAD. 'dummy' is
148 * supposed to be a pointer to the memory of the device being
149 * programmed by the UPM. The data in the MDR is written into
150 * memory and the MAD is incremented every time there's a read
151 * from 'dummy'. Unfortunately, the current prototype for this
152 * function doesn't allow for passing the address of this
153 * device, and changing the prototype will break a number lots
154 * of other code, so we need to use a round-about way of finding
155 * the value for 'dummy'.
157 * The value can be extracted from the base address bits of the
158 * Base Register (BR) associated with the specific UPM. To find
159 * that BR, we need to scan all 8 BRs until we find the one that
160 * has its MSEL bits matching the UPM we want. Once we know the
161 * right BR, we can extract the base address bits from it.
163 * The MxMR and the BR and OR of the chosen bank should all be
164 * configured before calling this function.
167 * upm: 0=UPMA, 1=UPMB, 2=UPMC
168 * table: Pointer to an array of values to program
169 * size: Number of elements in the array. Must be 64 or less.
171 void upmconfig (uint upm, uint *table, uint size)
173 #if defined(CONFIG_MPC834X)
174 volatile immap_t *immap = (immap_t *) CFG_IMMR;
175 volatile lbus83xx_t *lbus = &immap->lbus;
176 volatile uchar *dummy = NULL;
177 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
178 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
181 /* Scan all the banks to determine the base address of the device */
182 for (i = 0; i < 8; i++) {
183 if ((lbus->bank[i].br & BR_MSEL) == msel) {
184 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
190 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
194 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
195 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
197 for (i = 0; i < size; i++) {
198 lbus->mdr = table[i];
199 __asm__ __volatile__ ("sync");
200 *dummy; /* Write the value to memory and increment MAD */
201 __asm__ __volatile__ ("sync");
204 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
207 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
214 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
217 #ifndef MPC83xx_RESET
221 volatile immap_t *immap = (immap_t *) CFG_IMMR;
224 /* Interrupts and MMU off */
225 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
227 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
228 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
230 /* enable Reset Control Reg */
231 immap->reset.rpr = 0x52535445;
232 __asm__ __volatile__ ("sync");
233 __asm__ __volatile__ ("isync");
235 /* confirm Reset Control Reg is enabled */
236 while(!((immap->reset.rcer) & RCER_CRE));
238 printf("Resetting the board.");
243 /* perform reset, only one bit */
244 immap->reset.rcr = RCR_SWHR;
246 #else /* ! MPC83xx_RESET */
248 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
250 /* Interrupts and MMU off */
251 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
253 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
254 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
257 * Trying to execute the next instruction at a non-existing address
258 * should cause a machine check, resulting in reset
260 addr = CFG_RESET_ADDRESS;
262 printf("resetting the board.");
264 ((void (*)(void)) addr) ();
265 #endif /* MPC83xx_RESET */
272 * Get timebase clock frequency (like cpu_clk in Hz)
275 unsigned long get_tbclk(void)
279 tbclk = (gd->bus_clk + 3L) / 4L;
285 #if defined(CONFIG_WATCHDOG)
286 void watchdog_reset (void)
288 int re_enable = disable_interrupts();
290 /* Reset the 83xx watchdog */
291 volatile immap_t *immr = (immap_t *) CFG_IMMR;
292 immr->wdt.swsrr = 0x556c;
293 immr->wdt.swsrr = 0xaa39;
296 enable_interrupts ();
300 #if defined(CONFIG_OF_LIBFDT)
303 * Fixups to the fdt. If "create" is TRUE, the node is created
304 * unconditionally. If "create" is FALSE, the node is updated
305 * only if it already exists.
307 #define FT_UPDATE 0x00000000 /* update existing property only */
308 #define FT_CREATE 0x00000001 /* create property if it doesn't exist */
309 #define FT_BUSFREQ 0x00000002 /* source is bd->bi_busfreq */
310 #define FT_ENETADDR 0x00000004 /* source is bd->bi_enetaddr */
311 static const struct {
316 { FT_CREATE | FT_BUSFREQ,
320 { FT_CREATE | FT_BUSFREQ,
324 { FT_CREATE | FT_BUSFREQ,
325 "/" OF_SOC "/serial@4500/",
328 { FT_CREATE | FT_BUSFREQ,
329 "/" OF_SOC "/serial@4600/",
332 #ifdef CONFIG_MPC83XX_TSEC1
333 { FT_UPDATE | FT_ENETADDR,
334 "/" OF_SOC "/ethernet@24000,
337 { FT_UPDATE | FT_ENETADDR,
338 "/" OF_SOC "/ethernet@24000,
342 #ifdef CONFIG_MPC83XX_TSEC2
343 { FT_UPDATE | FT_ENETADDR,
344 "/" OF_SOC "/ethernet@25000,
347 { FT_UPDATE | FT_ENETADDR,
348 "/" OF_SOC "/ethernet@25000,
355 ft_cpu_setup(void *blob, bd_t *bd)
361 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
362 nodeoffset = fdt_path_offset (fdt, fixup_props[j].node);
363 if (nodeoffset >= 0) {
365 * If unconditional create or the property already exists...
367 if ((fixup_props[j].createflags & FT_CREATE) ||
368 (fdt_get_property(fdt, nodeoffset, fixup_props[j].prop, 0))) {
369 if (fixup_props[j].createflags & FT_BUSFREQ) {
372 tmp = cpu_to_be32(bd->bi_busfreq);
373 err = fdt_setprop(fdt, nodeoffset,
374 fixup_props[j].prop, &tmp, sizeof(tmp));
375 } else if (fixup_props[j].createflags & FT_ENETADDR) {
376 err = fdt_setprop(fdt, nodeoffset,
377 fixup_props[j].prop, bd->bi_enetaddr, 6);
379 printf("ft_cpu_setup: %s %s has no flag for the value to set\n",
381 fixup_props[j].prop);
384 printf("libfdt: %s %s returned %s\n",
394 #if defined(CONFIG_OF_FLAT_TREE)
396 ft_cpu_setup(void *blob, bd_t *bd)
402 clock = bd->bi_busfreq;
403 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
405 *p = cpu_to_be32(clock);
407 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
409 *p = cpu_to_be32(clock);
411 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
413 *p = cpu_to_be32(clock);
415 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
417 *p = cpu_to_be32(clock);
419 #ifdef CONFIG_MPC83XX_TSEC1
420 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
422 memcpy(p, bd->bi_enetaddr, 6);
424 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
426 memcpy(p, bd->bi_enetaddr, 6);
429 #ifdef CONFIG_MPC83XX_TSEC2
430 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
432 memcpy(p, bd->bi_enet1addr, 6);
434 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
436 memcpy(p, bd->bi_enet1addr, 6);
439 #ifdef CONFIG_UEC_ETH1
440 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
441 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
443 memcpy(p, bd->bi_enetaddr, 6);
445 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
447 memcpy(p, bd->bi_enetaddr, 6);
448 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
449 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
451 memcpy(p, bd->bi_enetaddr, 6);
453 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
455 memcpy(p, bd->bi_enetaddr, 6);
459 #ifdef CONFIG_UEC_ETH2
460 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
461 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
463 memcpy(p, bd->bi_enet1addr, 6);
465 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
467 memcpy(p, bd->bi_enet1addr, 6);
468 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
469 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
471 memcpy(p, bd->bi_enet1addr, 6);
473 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
475 memcpy(p, bd->bi_enet1addr, 6);
481 #if defined(CONFIG_DDR_ECC)
484 volatile immap_t *immap = (immap_t *)CFG_IMMR;
485 volatile dma83xx_t *dma = &immap->dma;
486 volatile u32 status = swab32(dma->dmasr0);
487 volatile u32 dmamr0 = swab32(dma->dmamr0);
491 /* initialize DMASARn, DMADAR and DMAABCRn */
492 dma->dmadar0 = (u32)0;
493 dma->dmasar0 = (u32)0;
496 __asm__ __volatile__ ("sync");
497 __asm__ __volatile__ ("isync");
500 dmamr0 &= ~DMA_CHANNEL_START;
501 dma->dmamr0 = swab32(dmamr0);
502 __asm__ __volatile__ ("sync");
503 __asm__ __volatile__ ("isync");
505 /* while the channel is busy, spin */
506 while(status & DMA_CHANNEL_BUSY) {
507 status = swab32(dma->dmasr0);
510 debug("DMA-init end\n");
515 volatile immap_t *immap = (immap_t *)CFG_IMMR;
516 volatile dma83xx_t *dma = &immap->dma;
517 volatile u32 status = swab32(dma->dmasr0);
518 volatile u32 byte_count = swab32(dma->dmabcr0);
520 /* while the channel is busy, spin */
521 while (status & DMA_CHANNEL_BUSY) {
522 status = swab32(dma->dmasr0);
525 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
526 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
532 int dma_xfer(void *dest, u32 count, void *src)
534 volatile immap_t *immap = (immap_t *)CFG_IMMR;
535 volatile dma83xx_t *dma = &immap->dma;
538 /* initialize DMASARn, DMADAR and DMAABCRn */
539 dma->dmadar0 = swab32((u32)dest);
540 dma->dmasar0 = swab32((u32)src);
541 dma->dmabcr0 = swab32(count);
543 __asm__ __volatile__ ("sync");
544 __asm__ __volatile__ ("isync");
546 /* init direct transfer, clear CS bit */
547 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
548 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
549 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
551 dma->dmamr0 = swab32(dmamr0);
553 __asm__ __volatile__ ("sync");
554 __asm__ __volatile__ ("isync");
556 /* set CS to start DMA transfer */
557 dmamr0 |= DMA_CHANNEL_START;
558 dma->dmamr0 = swab32(dmamr0);
559 __asm__ __volatile__ ("sync");
560 __asm__ __volatile__ ("isync");
562 return ((int)dma_check());
564 #endif /*CONFIG_DDR_ECC*/