2 * Copyright 2004 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * 20050101: Eran Liberty (liberty@freescale.com)
25 * Initial file creating (porting from 85XX & 8260)
29 * CPU specific code for the MPC83xx family.
31 * Derived from the MPC8260 and MPC85xx.
39 #include <asm/processor.h>
41 DECLARE_GLOBAL_DATA_PTR;
46 ulong clock = gd->cpu_clk;
50 if ((pvr & 0xFFFF0000) != PVR_83xx) {
51 puts("Not MPC83xx Family!!!\n");
55 puts("CPU: MPC83xx, ");
62 puts("Rev: Unknown\n");
63 return -1; /* Not sure what this is */
65 printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
66 (pvr & 0x0f), strmhz(buf, clock));
72 void upmconfig (uint upm, uint *table, uint size)
74 hang(); /* FIXME: upconfig() needed? */
79 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
86 volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
89 /* Interrupts and MMU off */
90 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
92 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
93 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
95 /* enable Reset Control Reg */
96 immap->reset.rpr = 0x52535445;
97 __asm__ __volatile__ ("sync");
98 __asm__ __volatile__ ("isync");
100 /* confirm Reset Control Reg is enabled */
101 while(!((immap->reset.rcer) & RCER_CRE));
103 printf("Resetting the board.");
108 /* perform reset, only one bit */
109 immap->reset.rcr = RCR_SWHR;
111 #else /* ! MPC83xx_RESET */
113 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
115 /* Interrupts and MMU off */
116 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
118 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
119 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
122 * Trying to execute the next instruction at a non-existing address
123 * should cause a machine check, resulting in reset
125 addr = CFG_RESET_ADDRESS;
127 printf("resetting the board.");
129 ((void (*)(void)) addr) ();
130 #endif /* MPC83xx_RESET */
137 * Get timebase clock frequency (like cpu_clk in Hz)
140 unsigned long get_tbclk(void)
144 tbclk = (gd->bus_clk + 3L) / 4L;
150 #if defined(CONFIG_WATCHDOG)
151 void watchdog_reset (void)
153 hang(); /* FIXME: implement watchdog_reset()? */
155 #endif /* CONFIG_WATCHDOG */
157 #if defined(CONFIG_OF_FLAT_TREE)
159 ft_cpu_setup(void *blob, bd_t *bd)
165 clock = bd->bi_busfreq;
166 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
168 *p = cpu_to_be32(clock);
170 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
172 *p = cpu_to_be32(clock);
174 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
176 *p = cpu_to_be32(clock);
178 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
180 *p = cpu_to_be32(clock);
182 #ifdef CONFIG_MPC83XX_TSEC1
183 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
184 memcpy(p, bd->bi_enetaddr, 6);
187 #ifdef CONFIG_MPC83XX_TSEC2
188 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
189 memcpy(p, bd->bi_enet1addr, 6);
194 #if defined(CONFIG_DDR_ECC)
197 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
198 volatile dma8349_t *dma = &immap->dma;
199 volatile u32 status = swab32(dma->dmasr0);
200 volatile u32 dmamr0 = swab32(dma->dmamr0);
204 /* initialize DMASARn, DMADAR and DMAABCRn */
205 dma->dmadar0 = (u32)0;
206 dma->dmasar0 = (u32)0;
209 __asm__ __volatile__ ("sync");
210 __asm__ __volatile__ ("isync");
213 dmamr0 &= ~DMA_CHANNEL_START;
214 dma->dmamr0 = swab32(dmamr0);
215 __asm__ __volatile__ ("sync");
216 __asm__ __volatile__ ("isync");
218 /* while the channel is busy, spin */
219 while(status & DMA_CHANNEL_BUSY) {
220 status = swab32(dma->dmasr0);
223 debug("DMA-init end\n");
228 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
229 volatile dma8349_t *dma = &immap->dma;
230 volatile u32 status = swab32(dma->dmasr0);
231 volatile u32 byte_count = swab32(dma->dmabcr0);
233 /* while the channel is busy, spin */
234 while (status & DMA_CHANNEL_BUSY) {
235 status = swab32(dma->dmasr0);
238 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
239 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
245 int dma_xfer(void *dest, u32 count, void *src)
247 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
248 volatile dma8349_t *dma = &immap->dma;
251 /* initialize DMASARn, DMADAR and DMAABCRn */
252 dma->dmadar0 = swab32((u32)dest);
253 dma->dmasar0 = swab32((u32)src);
254 dma->dmabcr0 = swab32(count);
256 __asm__ __volatile__ ("sync");
257 __asm__ __volatile__ ("isync");
259 /* init direct transfer, clear CS bit */
260 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
261 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
262 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
264 dma->dmamr0 = swab32(dmamr0);
266 __asm__ __volatile__ ("sync");
267 __asm__ __volatile__ ("isync");
269 /* set CS to start DMA transfer */
270 dmamr0 |= DMA_CHANNEL_START;
271 dma->dmamr0 = swab32(dmamr0);
272 __asm__ __volatile__ ("sync");
273 __asm__ __volatile__ ("isync");
275 return ((int)dma_check());
277 #endif /*CONFIG_DDR_ECC*/