2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 #elif defined(CONFIG_OF_LIBFDT)
38 #include <fdt_support.h>
41 DECLARE_GLOBAL_DATA_PTR;
45 volatile immap_t *immr;
46 ulong clock = gd->cpu_clk;
51 immr = (immap_t *)CFG_IMMR;
55 switch (pvr & 0xffff0000) {
69 printf("Unknown core, ");
72 spridr = immr->sysconf.spridr;
84 case SPR_8347E_REV10_TBGA:
85 case SPR_8347E_REV11_TBGA:
86 case SPR_8347E_REV31_TBGA:
87 case SPR_8347E_REV10_PBGA:
88 case SPR_8347E_REV11_PBGA:
89 case SPR_8347E_REV31_PBGA:
92 case SPR_8347_REV10_TBGA:
93 case SPR_8347_REV11_TBGA:
94 case SPR_8347_REV31_TBGA:
95 case SPR_8347_REV10_PBGA:
96 case SPR_8347_REV11_PBGA:
97 case SPR_8347_REV31_PBGA:
100 case SPR_8343E_REV10:
101 case SPR_8343E_REV11:
102 case SPR_8343E_REV31:
110 case SPR_8360E_REV10:
111 case SPR_8360E_REV11:
112 case SPR_8360E_REV12:
113 case SPR_8360E_REV20:
114 case SPR_8360E_REV21:
124 case SPR_8323E_REV10:
125 case SPR_8323E_REV11:
132 case SPR_8321E_REV10:
133 case SPR_8321E_REV11:
143 case SPR_8311E_REV10:
149 case SPR_8313E_REV10:
153 printf("Rev: Unknown revision number:%08x\n"
154 "Warning: Unsupported cpu revision!\n",spridr);
158 #if defined(CONFIG_MPC834X)
159 /* Multiple revisons of 834x processors may have the same SPRIDR value.
160 * So use PVR to identify the revision number.
162 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
164 printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
166 printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
173 * Program a UPM with the code supplied in the table.
175 * The 'dummy' variable is used to increment the MAD. 'dummy' is
176 * supposed to be a pointer to the memory of the device being
177 * programmed by the UPM. The data in the MDR is written into
178 * memory and the MAD is incremented every time there's a read
179 * from 'dummy'. Unfortunately, the current prototype for this
180 * function doesn't allow for passing the address of this
181 * device, and changing the prototype will break a number lots
182 * of other code, so we need to use a round-about way of finding
183 * the value for 'dummy'.
185 * The value can be extracted from the base address bits of the
186 * Base Register (BR) associated with the specific UPM. To find
187 * that BR, we need to scan all 8 BRs until we find the one that
188 * has its MSEL bits matching the UPM we want. Once we know the
189 * right BR, we can extract the base address bits from it.
191 * The MxMR and the BR and OR of the chosen bank should all be
192 * configured before calling this function.
195 * upm: 0=UPMA, 1=UPMB, 2=UPMC
196 * table: Pointer to an array of values to program
197 * size: Number of elements in the array. Must be 64 or less.
199 void upmconfig (uint upm, uint *table, uint size)
201 #if defined(CONFIG_MPC834X)
202 volatile immap_t *immap = (immap_t *) CFG_IMMR;
203 volatile lbus83xx_t *lbus = &immap->lbus;
204 volatile uchar *dummy = NULL;
205 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
206 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
209 /* Scan all the banks to determine the base address of the device */
210 for (i = 0; i < 8; i++) {
211 if ((lbus->bank[i].br & BR_MSEL) == msel) {
212 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
218 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
222 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
223 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
225 for (i = 0; i < size; i++) {
226 lbus->mdr = table[i];
227 __asm__ __volatile__ ("sync");
228 *dummy; /* Write the value to memory and increment MAD */
229 __asm__ __volatile__ ("sync");
232 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
235 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
242 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
245 #ifndef MPC83xx_RESET
249 volatile immap_t *immap = (immap_t *) CFG_IMMR;
252 /* Interrupts and MMU off */
253 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
255 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
256 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
258 /* enable Reset Control Reg */
259 immap->reset.rpr = 0x52535445;
260 __asm__ __volatile__ ("sync");
261 __asm__ __volatile__ ("isync");
263 /* confirm Reset Control Reg is enabled */
264 while(!((immap->reset.rcer) & RCER_CRE));
266 printf("Resetting the board.");
271 /* perform reset, only one bit */
272 immap->reset.rcr = RCR_SWHR;
274 #else /* ! MPC83xx_RESET */
276 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
278 /* Interrupts and MMU off */
279 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
281 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
282 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
285 * Trying to execute the next instruction at a non-existing address
286 * should cause a machine check, resulting in reset
288 addr = CFG_RESET_ADDRESS;
290 printf("resetting the board.");
292 ((void (*)(void)) addr) ();
293 #endif /* MPC83xx_RESET */
300 * Get timebase clock frequency (like cpu_clk in Hz)
303 unsigned long get_tbclk(void)
307 tbclk = (gd->bus_clk + 3L) / 4L;
313 #if defined(CONFIG_WATCHDOG)
314 void watchdog_reset (void)
316 int re_enable = disable_interrupts();
318 /* Reset the 83xx watchdog */
319 volatile immap_t *immr = (immap_t *) CFG_IMMR;
320 immr->wdt.swsrr = 0x556c;
321 immr->wdt.swsrr = 0xaa39;
324 enable_interrupts ();
328 #if defined(CONFIG_OF_LIBFDT)
331 * "Setter" functions used to add/modify FDT entries.
333 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
335 /* Fix it up if it exists, don't create it if it doesn't exist */
336 if (fdt_get_property(blob, nodeoffset, name, 0)) {
337 return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
341 #ifdef CONFIG_HAS_ETH1
342 /* second onboard ethernet port */
343 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
345 /* Fix it up if it exists, don't create it if it doesn't exist */
346 if (fdt_get_property(blob, nodeoffset, name, 0)) {
347 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
352 #ifdef CONFIG_HAS_ETH2
353 /* third onboard ethernet port */
354 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
356 /* Fix it up if it exists, don't create it if it doesn't exist */
357 if (fdt_get_property(blob, nodeoffset, name, 0)) {
358 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
363 #ifdef CONFIG_HAS_ETH3
364 /* fourth onboard ethernet port */
365 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
367 /* Fix it up if it exists, don't create it if it doesn't exist */
368 if (fdt_get_property(blob, nodeoffset, name, 0)) {
369 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
375 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
378 /* Create or update the property */
379 tmp = cpu_to_be32(bd->bi_busfreq);
380 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
383 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
386 /* Create or update the property */
387 tmp = cpu_to_be32(OF_TBCLK);
388 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
392 static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
395 /* Create or update the property */
396 tmp = cpu_to_be32(gd->core_clk);
397 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
401 static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
404 /* Create or update the property */
405 tmp = cpu_to_be32(gd->qe_clk);
406 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
409 static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
412 /* Create or update the property */
413 tmp = cpu_to_be32(gd->brg_clk);
414 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
421 static const struct {
424 int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
427 "timebase-frequency",
442 { "/" OF_SOC "/serial@4500",
446 { "/" OF_SOC "/serial@4600",
451 { "/" OF_SOC "/ethernet@24000",
455 { "/" OF_SOC "/ethernet@24000",
461 { "/" OF_SOC "/ethernet@25000",
465 { "/" OF_SOC "/ethernet@25000",
479 #ifdef CONFIG_UEC_ETH1
480 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
481 { "/" OF_QE "/ucc@2000",
485 { "/" OF_QE "/ucc@2000",
489 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
490 { "/" OF_QE "/ucc@2200",
494 { "/" OF_QE "/ucc@2200",
499 #endif /* CONFIG_UEC_ETH1 */
500 #ifdef CONFIG_UEC_ETH2
501 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
502 { "/" OF_QE "/ucc@3000",
506 { "/" OF_QE "/ucc@3000",
510 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
511 { "/" OF_QE "/ucc@3200",
515 { "/" OF_QE "/ucc@3200",
520 #endif /* CONFIG_UEC_ETH2 */
521 #endif /* CONFIG_QE */
525 ft_cpu_setup(void *blob, bd_t *bd)
531 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
532 nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
533 if (nodeoffset >= 0) {
534 err = fixup_props[j].set_fn(blob, nodeoffset,
535 fixup_props[j].prop, bd);
537 debug("Problem setting %s = %s: %s\n",
538 fixup_props[j].node, fixup_props[j].prop,
541 debug("Couldn't find %s: %s\n",
542 fixup_props[j].node, fdt_strerror(nodeoffset));
546 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
548 #elif defined(CONFIG_OF_FLAT_TREE)
550 ft_cpu_setup(void *blob, bd_t *bd)
556 clock = bd->bi_busfreq;
557 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
559 *p = cpu_to_be32(clock);
561 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
563 *p = cpu_to_be32(clock);
565 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
567 *p = cpu_to_be32(clock);
569 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
571 *p = cpu_to_be32(clock);
574 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
576 memcpy(p, bd->bi_enetaddr, 6);
578 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
580 memcpy(p, bd->bi_enetaddr, 6);
584 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
586 memcpy(p, bd->bi_enet1addr, 6);
588 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
590 memcpy(p, bd->bi_enet1addr, 6);
593 #ifdef CONFIG_UEC_ETH1
594 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
595 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
597 memcpy(p, bd->bi_enetaddr, 6);
599 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
601 memcpy(p, bd->bi_enetaddr, 6);
602 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
603 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
605 memcpy(p, bd->bi_enetaddr, 6);
607 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
609 memcpy(p, bd->bi_enetaddr, 6);
613 #ifdef CONFIG_UEC_ETH2
614 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
615 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
617 memcpy(p, bd->bi_enet1addr, 6);
619 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
621 memcpy(p, bd->bi_enet1addr, 6);
622 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
623 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
625 memcpy(p, bd->bi_enet1addr, 6);
627 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
629 memcpy(p, bd->bi_enet1addr, 6);
635 #if defined(CONFIG_DDR_ECC)
638 volatile immap_t *immap = (immap_t *)CFG_IMMR;
639 volatile dma83xx_t *dma = &immap->dma;
640 volatile u32 status = swab32(dma->dmasr0);
641 volatile u32 dmamr0 = swab32(dma->dmamr0);
645 /* initialize DMASARn, DMADAR and DMAABCRn */
646 dma->dmadar0 = (u32)0;
647 dma->dmasar0 = (u32)0;
650 __asm__ __volatile__ ("sync");
651 __asm__ __volatile__ ("isync");
654 dmamr0 &= ~DMA_CHANNEL_START;
655 dma->dmamr0 = swab32(dmamr0);
656 __asm__ __volatile__ ("sync");
657 __asm__ __volatile__ ("isync");
659 /* while the channel is busy, spin */
660 while(status & DMA_CHANNEL_BUSY) {
661 status = swab32(dma->dmasr0);
664 debug("DMA-init end\n");
669 volatile immap_t *immap = (immap_t *)CFG_IMMR;
670 volatile dma83xx_t *dma = &immap->dma;
671 volatile u32 status = swab32(dma->dmasr0);
672 volatile u32 byte_count = swab32(dma->dmabcr0);
674 /* while the channel is busy, spin */
675 while (status & DMA_CHANNEL_BUSY) {
676 status = swab32(dma->dmasr0);
679 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
680 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
686 int dma_xfer(void *dest, u32 count, void *src)
688 volatile immap_t *immap = (immap_t *)CFG_IMMR;
689 volatile dma83xx_t *dma = &immap->dma;
692 /* initialize DMASARn, DMADAR and DMAABCRn */
693 dma->dmadar0 = swab32((u32)dest);
694 dma->dmasar0 = swab32((u32)src);
695 dma->dmabcr0 = swab32(count);
697 __asm__ __volatile__ ("sync");
698 __asm__ __volatile__ ("isync");
700 /* init direct transfer, clear CS bit */
701 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
702 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
703 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
705 dma->dmamr0 = swab32(dmamr0);
707 __asm__ __volatile__ ("sync");
708 __asm__ __volatile__ ("isync");
710 /* set CS to start DMA transfer */
711 dmamr0 |= DMA_CHANNEL_START;
712 dma->dmamr0 = swab32(dmamr0);
713 __asm__ __volatile__ ("sync");
714 __asm__ __volatile__ ("isync");
716 return ((int)dma_check());
718 #endif /*CONFIG_DDR_ECC*/