2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
34 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
41 volatile immap_t *immr;
42 ulong clock = gd->cpu_clk;
47 immr = (immap_t *)CFG_IMMR;
49 if ((pvr & 0xFFFF0000) != PVR_83xx) {
50 puts("Not MPC83xx Family!!!\n");
54 spridr = immr->sysconf.spridr;
65 case SPR_8347E_REV10_TBGA:
66 case SPR_8347E_REV11_TBGA:
67 case SPR_8347E_REV10_PBGA:
68 case SPR_8347E_REV11_PBGA:
71 case SPR_8347_REV10_TBGA:
72 case SPR_8347_REV11_TBGA:
73 case SPR_8347_REV10_PBGA:
74 case SPR_8347_REV11_PBGA:
103 case SPR_8321E_REV10:
104 case SPR_8321E_REV11:
112 puts("Rev: Unknown\n");
113 return -1; /* Not sure what this is */
116 #if defined(CONFIG_MPC834X)
117 printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
119 printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
126 * Program a UPM with the code supplied in the table.
128 * The 'dummy' variable is used to increment the MAD. 'dummy' is
129 * supposed to be a pointer to the memory of the device being
130 * programmed by the UPM. The data in the MDR is written into
131 * memory and the MAD is incremented every time there's a read
132 * from 'dummy'. Unfortunately, the current prototype for this
133 * function doesn't allow for passing the address of this
134 * device, and changing the prototype will break a number lots
135 * of other code, so we need to use a round-about way of finding
136 * the value for 'dummy'.
138 * The value can be extracted from the base address bits of the
139 * Base Register (BR) associated with the specific UPM. To find
140 * that BR, we need to scan all 8 BRs until we find the one that
141 * has its MSEL bits matching the UPM we want. Once we know the
142 * right BR, we can extract the base address bits from it.
144 * The MxMR and the BR and OR of the chosen bank should all be
145 * configured before calling this function.
148 * upm: 0=UPMA, 1=UPMB, 2=UPMC
149 * table: Pointer to an array of values to program
150 * size: Number of elements in the array. Must be 64 or less.
152 void upmconfig (uint upm, uint *table, uint size)
154 #if defined(CONFIG_MPC834X)
155 volatile immap_t *immap = (immap_t *) CFG_IMMR;
156 volatile lbus83xx_t *lbus = &immap->lbus;
157 volatile uchar *dummy = NULL;
158 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
159 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
162 /* Scan all the banks to determine the base address of the device */
163 for (i = 0; i < 8; i++) {
164 if ((lbus->bank[i].br & BR_MSEL) == msel) {
165 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
171 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
175 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
176 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
178 for (i = 0; i < size; i++) {
179 lbus->mdr = table[i];
180 __asm__ __volatile__ ("sync");
181 *dummy; /* Write the value to memory and increment MAD */
182 __asm__ __volatile__ ("sync");
185 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
188 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
195 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
198 #ifndef MPC83xx_RESET
202 volatile immap_t *immap = (immap_t *) CFG_IMMR;
205 /* Interrupts and MMU off */
206 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
208 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
209 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
211 /* enable Reset Control Reg */
212 immap->reset.rpr = 0x52535445;
213 __asm__ __volatile__ ("sync");
214 __asm__ __volatile__ ("isync");
216 /* confirm Reset Control Reg is enabled */
217 while(!((immap->reset.rcer) & RCER_CRE));
219 printf("Resetting the board.");
224 /* perform reset, only one bit */
225 immap->reset.rcr = RCR_SWHR;
227 #else /* ! MPC83xx_RESET */
229 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
231 /* Interrupts and MMU off */
232 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
234 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
235 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
238 * Trying to execute the next instruction at a non-existing address
239 * should cause a machine check, resulting in reset
241 addr = CFG_RESET_ADDRESS;
243 printf("resetting the board.");
245 ((void (*)(void)) addr) ();
246 #endif /* MPC83xx_RESET */
253 * Get timebase clock frequency (like cpu_clk in Hz)
256 unsigned long get_tbclk(void)
260 tbclk = (gd->bus_clk + 3L) / 4L;
266 #if defined(CONFIG_WATCHDOG)
267 void watchdog_reset (void)
269 int re_enable = disable_interrupts();
271 /* Reset the 83xx watchdog */
272 volatile immap_t *immr = (immap_t *) CFG_IMMR;
273 immr->wdt.swsrr = 0x556c;
274 immr->wdt.swsrr = 0xaa39;
277 enable_interrupts ();
281 #if defined(CONFIG_OF_FLAT_TREE)
283 ft_cpu_setup(void *blob, bd_t *bd)
289 clock = bd->bi_busfreq;
290 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
292 *p = cpu_to_be32(clock);
294 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
296 *p = cpu_to_be32(clock);
298 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
300 *p = cpu_to_be32(clock);
302 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
304 *p = cpu_to_be32(clock);
306 #ifdef CONFIG_MPC83XX_TSEC1
307 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
309 memcpy(p, bd->bi_enetaddr, 6);
312 #ifdef CONFIG_MPC83XX_TSEC2
313 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
315 memcpy(p, bd->bi_enet1addr, 6);
320 #if defined(CONFIG_DDR_ECC)
323 volatile immap_t *immap = (immap_t *)CFG_IMMR;
324 volatile dma83xx_t *dma = &immap->dma;
325 volatile u32 status = swab32(dma->dmasr0);
326 volatile u32 dmamr0 = swab32(dma->dmamr0);
330 /* initialize DMASARn, DMADAR and DMAABCRn */
331 dma->dmadar0 = (u32)0;
332 dma->dmasar0 = (u32)0;
335 __asm__ __volatile__ ("sync");
336 __asm__ __volatile__ ("isync");
339 dmamr0 &= ~DMA_CHANNEL_START;
340 dma->dmamr0 = swab32(dmamr0);
341 __asm__ __volatile__ ("sync");
342 __asm__ __volatile__ ("isync");
344 /* while the channel is busy, spin */
345 while(status & DMA_CHANNEL_BUSY) {
346 status = swab32(dma->dmasr0);
349 debug("DMA-init end\n");
354 volatile immap_t *immap = (immap_t *)CFG_IMMR;
355 volatile dma83xx_t *dma = &immap->dma;
356 volatile u32 status = swab32(dma->dmasr0);
357 volatile u32 byte_count = swab32(dma->dmabcr0);
359 /* while the channel is busy, spin */
360 while (status & DMA_CHANNEL_BUSY) {
361 status = swab32(dma->dmasr0);
364 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
365 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
371 int dma_xfer(void *dest, u32 count, void *src)
373 volatile immap_t *immap = (immap_t *)CFG_IMMR;
374 volatile dma83xx_t *dma = &immap->dma;
377 /* initialize DMASARn, DMADAR and DMAABCRn */
378 dma->dmadar0 = swab32((u32)dest);
379 dma->dmasar0 = swab32((u32)src);
380 dma->dmabcr0 = swab32(count);
382 __asm__ __volatile__ ("sync");
383 __asm__ __volatile__ ("isync");
385 /* init direct transfer, clear CS bit */
386 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
387 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
388 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
390 dma->dmamr0 = swab32(dmamr0);
392 __asm__ __volatile__ ("sync");
393 __asm__ __volatile__ ("isync");
395 /* set CS to start DMA transfer */
396 dmamr0 |= DMA_CHANNEL_START;
397 dma->dmamr0 = swab32(dmamr0);
398 __asm__ __volatile__ ("sync");
399 __asm__ __volatile__ ("isync");
401 return ((int)dma_check());
403 #endif /*CONFIG_DDR_ECC*/