2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 #elif defined(CONFIG_OF_LIBFDT)
38 #include <libfdt_env.h>
41 DECLARE_GLOBAL_DATA_PTR;
46 volatile immap_t *immr;
47 ulong clock = gd->cpu_clk;
52 immr = (immap_t *)CFG_IMMR;
56 switch (pvr & 0xffff0000) {
70 printf("Unknown core, ");
73 spridr = immr->sysconf.spridr;
85 case SPR_8347E_REV10_TBGA:
86 case SPR_8347E_REV11_TBGA:
87 case SPR_8347E_REV31_TBGA:
88 case SPR_8347E_REV10_PBGA:
89 case SPR_8347E_REV11_PBGA:
90 case SPR_8347E_REV31_PBGA:
93 case SPR_8347_REV10_TBGA:
94 case SPR_8347_REV11_TBGA:
95 case SPR_8347_REV31_TBGA:
96 case SPR_8347_REV10_PBGA:
97 case SPR_8347_REV11_PBGA:
98 case SPR_8347_REV31_PBGA:
101 case SPR_8343E_REV10:
102 case SPR_8343E_REV11:
103 case SPR_8343E_REV31:
111 case SPR_8360E_REV10:
112 case SPR_8360E_REV11:
113 case SPR_8360E_REV12:
114 case SPR_8360E_REV20:
115 case SPR_8360E_REV21:
125 case SPR_8323E_REV10:
126 case SPR_8323E_REV11:
133 case SPR_8321E_REV10:
134 case SPR_8321E_REV11:
144 case SPR_8311E_REV10:
150 case SPR_8313E_REV10:
154 printf("Rev: Unknown revision number:%08x\n"
155 "Warning: Unsupported cpu revision!\n",spridr);
159 #if defined(CONFIG_MPC834X)
160 /* Multiple revisons of 834x processors may have the same SPRIDR value.
161 * So use PVR to identify the revision number.
163 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
165 printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
167 printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
174 * Program a UPM with the code supplied in the table.
176 * The 'dummy' variable is used to increment the MAD. 'dummy' is
177 * supposed to be a pointer to the memory of the device being
178 * programmed by the UPM. The data in the MDR is written into
179 * memory and the MAD is incremented every time there's a read
180 * from 'dummy'. Unfortunately, the current prototype for this
181 * function doesn't allow for passing the address of this
182 * device, and changing the prototype will break a number lots
183 * of other code, so we need to use a round-about way of finding
184 * the value for 'dummy'.
186 * The value can be extracted from the base address bits of the
187 * Base Register (BR) associated with the specific UPM. To find
188 * that BR, we need to scan all 8 BRs until we find the one that
189 * has its MSEL bits matching the UPM we want. Once we know the
190 * right BR, we can extract the base address bits from it.
192 * The MxMR and the BR and OR of the chosen bank should all be
193 * configured before calling this function.
196 * upm: 0=UPMA, 1=UPMB, 2=UPMC
197 * table: Pointer to an array of values to program
198 * size: Number of elements in the array. Must be 64 or less.
200 void upmconfig (uint upm, uint *table, uint size)
202 #if defined(CONFIG_MPC834X)
203 volatile immap_t *immap = (immap_t *) CFG_IMMR;
204 volatile lbus83xx_t *lbus = &immap->lbus;
205 volatile uchar *dummy = NULL;
206 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
207 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
210 /* Scan all the banks to determine the base address of the device */
211 for (i = 0; i < 8; i++) {
212 if ((lbus->bank[i].br & BR_MSEL) == msel) {
213 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
219 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
223 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
224 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
226 for (i = 0; i < size; i++) {
227 lbus->mdr = table[i];
228 __asm__ __volatile__ ("sync");
229 *dummy; /* Write the value to memory and increment MAD */
230 __asm__ __volatile__ ("sync");
233 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
236 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
243 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
246 #ifndef MPC83xx_RESET
250 volatile immap_t *immap = (immap_t *) CFG_IMMR;
253 /* Interrupts and MMU off */
254 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
256 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
257 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
259 /* enable Reset Control Reg */
260 immap->reset.rpr = 0x52535445;
261 __asm__ __volatile__ ("sync");
262 __asm__ __volatile__ ("isync");
264 /* confirm Reset Control Reg is enabled */
265 while(!((immap->reset.rcer) & RCER_CRE));
267 printf("Resetting the board.");
272 /* perform reset, only one bit */
273 immap->reset.rcr = RCR_SWHR;
275 #else /* ! MPC83xx_RESET */
277 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
279 /* Interrupts and MMU off */
280 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
282 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
283 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
286 * Trying to execute the next instruction at a non-existing address
287 * should cause a machine check, resulting in reset
289 addr = CFG_RESET_ADDRESS;
291 printf("resetting the board.");
293 ((void (*)(void)) addr) ();
294 #endif /* MPC83xx_RESET */
301 * Get timebase clock frequency (like cpu_clk in Hz)
304 unsigned long get_tbclk(void)
308 tbclk = (gd->bus_clk + 3L) / 4L;
314 #if defined(CONFIG_WATCHDOG)
315 void watchdog_reset (void)
317 int re_enable = disable_interrupts();
319 /* Reset the 83xx watchdog */
320 volatile immap_t *immr = (immap_t *) CFG_IMMR;
321 immr->wdt.swsrr = 0x556c;
322 immr->wdt.swsrr = 0xaa39;
325 enable_interrupts ();
329 #if defined(CONFIG_OF_LIBFDT)
332 * "Setter" functions used to add/modify FDT entries.
334 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
337 * Fix it up if it exists, don't create it if it doesn't exist.
339 if (fdt_get_property(blob, nodeoffset, name, 0)) {
340 return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
344 #ifdef CONFIG_HAS_ETH1
345 /* second onboard ethernet port */
346 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
349 * Fix it up if it exists, don't create it if it doesn't exist.
351 if (fdt_get_property(blob, nodeoffset, name, 0)) {
352 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
357 #ifdef CONFIG_HAS_ETH2
358 /* third onboard ethernet port */
359 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
362 * Fix it up if it exists, don't create it if it doesn't exist.
364 if (fdt_get_property(blob, nodeoffset, name, 0)) {
365 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
370 #ifdef CONFIG_HAS_ETH3
371 /* fourth onboard ethernet port */
372 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
375 * Fix it up if it exists, don't create it if it doesn't exist.
377 if (fdt_get_property(blob, nodeoffset, name, 0)) {
378 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
384 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
388 * Create or update the property.
390 tmp = cpu_to_be32(bd->bi_busfreq);
391 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
394 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
398 * Create or update the property.
400 tmp = cpu_to_be32(OF_TBCLK);
401 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
408 static const struct {
411 int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
414 "timebase-frequency",
425 { "/" OF_SOC "/serial@4500",
429 { "/" OF_SOC "/serial@4600",
434 { "/" OF_SOC "/ethernet@24000",
438 { "/" OF_SOC "/ethernet@24000",
444 { "/" OF_SOC "/ethernet@25000",
448 { "/" OF_SOC "/ethernet@25000",
453 #ifdef CONFIG_UEC_ETH1
454 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
455 { "/" OF_QE "/ucc@2000",
459 { "/" OF_QE "/ucc@2000",
463 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
464 { "/" OF_QE "/ucc@2200",
468 { "/" OF_QE "/ucc@2200",
473 #endif /* CONFIG_UEC_ETH1 */
474 #ifdef CONFIG_UEC_ETH2
475 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
476 { "/" OF_QE "/ucc@3000",
480 { "/" OF_QE "/ucc@3000",
484 #elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
485 { "/" OF_QE "/ucc@3200",
489 { "/" OF_QE "/ucc@3200",
494 #endif /* CONFIG_UEC_ETH2 */
498 ft_cpu_setup(void *blob, bd_t *bd)
504 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
505 nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node);
506 if (nodeoffset >= 0) {
507 err = fixup_props[j].set_fn(blob, nodeoffset,
508 fixup_props[j].prop, bd);
510 debug("Problem setting %s = %s: %s\n",
515 debug("Couldn't find %s: %s\n",
517 fdt_strerror(nodeoffset));
521 #elif defined(CONFIG_OF_FLAT_TREE)
523 ft_cpu_setup(void *blob, bd_t *bd)
529 clock = bd->bi_busfreq;
530 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
532 *p = cpu_to_be32(clock);
534 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
536 *p = cpu_to_be32(clock);
538 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
540 *p = cpu_to_be32(clock);
542 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
544 *p = cpu_to_be32(clock);
547 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
549 memcpy(p, bd->bi_enetaddr, 6);
551 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
553 memcpy(p, bd->bi_enetaddr, 6);
557 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
559 memcpy(p, bd->bi_enet1addr, 6);
561 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
563 memcpy(p, bd->bi_enet1addr, 6);
566 #ifdef CONFIG_UEC_ETH1
567 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
568 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
570 memcpy(p, bd->bi_enetaddr, 6);
572 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
574 memcpy(p, bd->bi_enetaddr, 6);
575 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
576 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
578 memcpy(p, bd->bi_enetaddr, 6);
580 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
582 memcpy(p, bd->bi_enetaddr, 6);
586 #ifdef CONFIG_UEC_ETH2
587 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
588 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
590 memcpy(p, bd->bi_enet1addr, 6);
592 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
594 memcpy(p, bd->bi_enet1addr, 6);
595 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
596 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
598 memcpy(p, bd->bi_enet1addr, 6);
600 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
602 memcpy(p, bd->bi_enet1addr, 6);
608 #if defined(CONFIG_DDR_ECC)
611 volatile immap_t *immap = (immap_t *)CFG_IMMR;
612 volatile dma83xx_t *dma = &immap->dma;
613 volatile u32 status = swab32(dma->dmasr0);
614 volatile u32 dmamr0 = swab32(dma->dmamr0);
618 /* initialize DMASARn, DMADAR and DMAABCRn */
619 dma->dmadar0 = (u32)0;
620 dma->dmasar0 = (u32)0;
623 __asm__ __volatile__ ("sync");
624 __asm__ __volatile__ ("isync");
627 dmamr0 &= ~DMA_CHANNEL_START;
628 dma->dmamr0 = swab32(dmamr0);
629 __asm__ __volatile__ ("sync");
630 __asm__ __volatile__ ("isync");
632 /* while the channel is busy, spin */
633 while(status & DMA_CHANNEL_BUSY) {
634 status = swab32(dma->dmasr0);
637 debug("DMA-init end\n");
642 volatile immap_t *immap = (immap_t *)CFG_IMMR;
643 volatile dma83xx_t *dma = &immap->dma;
644 volatile u32 status = swab32(dma->dmasr0);
645 volatile u32 byte_count = swab32(dma->dmabcr0);
647 /* while the channel is busy, spin */
648 while (status & DMA_CHANNEL_BUSY) {
649 status = swab32(dma->dmasr0);
652 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
653 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
659 int dma_xfer(void *dest, u32 count, void *src)
661 volatile immap_t *immap = (immap_t *)CFG_IMMR;
662 volatile dma83xx_t *dma = &immap->dma;
665 /* initialize DMASARn, DMADAR and DMAABCRn */
666 dma->dmadar0 = swab32((u32)dest);
667 dma->dmasar0 = swab32((u32)src);
668 dma->dmabcr0 = swab32(count);
670 __asm__ __volatile__ ("sync");
671 __asm__ __volatile__ ("isync");
673 /* init direct transfer, clear CS bit */
674 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
675 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
676 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
678 dma->dmamr0 = swab32(dmamr0);
680 __asm__ __volatile__ ("sync");
681 __asm__ __volatile__ ("isync");
683 /* set CS to start DMA transfer */
684 dmamr0 |= DMA_CHANNEL_START;
685 dma->dmamr0 = swab32(dmamr0);
686 __asm__ __volatile__ ("sync");
687 __asm__ __volatile__ ("isync");
689 return ((int)dma_check());
691 #endif /*CONFIG_DDR_ECC*/