2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
38 DECLARE_GLOBAL_DATA_PTR;
42 volatile immap_t *immr;
43 ulong clock = gd->cpu_clk;
49 const struct cpu_type {
52 } cpu_type_list [] = {
60 CPU_TYPE_ENTRY(8347_TBGA_),
61 CPU_TYPE_ENTRY(8347_PBGA_),
63 CPU_TYPE_ENTRY(8358_TBGA_),
64 CPU_TYPE_ENTRY(8358_PBGA_),
71 immr = (immap_t *)CONFIG_SYS_IMMR;
75 switch (pvr & 0xffff0000) {
93 printf("Unknown core, ");
96 spridr = immr->sysconf.spridr;
98 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
99 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
101 puts(cpu_type_list[i].name);
102 if (IS_E_PROCESSOR(spridr))
104 if (REVID_MAJOR(spridr) >= 2)
106 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
107 REVID_MINOR(spridr));
111 if (i == ARRAY_SIZE(cpu_type_list))
112 printf("(SPRIDR %08x unknown), ", spridr);
114 printf(" at %s MHz, ", strmhz(buf, clock));
116 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
123 * Program a UPM with the code supplied in the table.
125 * The 'dummy' variable is used to increment the MAD. 'dummy' is
126 * supposed to be a pointer to the memory of the device being
127 * programmed by the UPM. The data in the MDR is written into
128 * memory and the MAD is incremented every time there's a write
129 * to 'dummy'. Unfortunately, the current prototype for this
130 * function doesn't allow for passing the address of this
131 * device, and changing the prototype will break a number lots
132 * of other code, so we need to use a round-about way of finding
133 * the value for 'dummy'.
135 * The value can be extracted from the base address bits of the
136 * Base Register (BR) associated with the specific UPM. To find
137 * that BR, we need to scan all 8 BRs until we find the one that
138 * has its MSEL bits matching the UPM we want. Once we know the
139 * right BR, we can extract the base address bits from it.
141 * The MxMR and the BR and OR of the chosen bank should all be
142 * configured before calling this function.
145 * upm: 0=UPMA, 1=UPMB, 2=UPMC
146 * table: Pointer to an array of values to program
147 * size: Number of elements in the array. Must be 64 or less.
149 void upmconfig (uint upm, uint *table, uint size)
151 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
152 volatile fsl_lbus_t *lbus = &immap->lbus;
153 volatile uchar *dummy = NULL;
154 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
155 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
158 /* Scan all the banks to determine the base address of the device */
159 for (i = 0; i < 8; i++) {
160 if ((lbus->bank[i].br & BR_MSEL) == msel) {
161 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
167 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
171 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
172 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
174 for (i = 0; i < size; i++) {
175 lbus->mdr = table[i];
176 __asm__ __volatile__ ("sync");
177 *dummy = 0; /* Write the value to memory and increment MAD */
178 __asm__ __volatile__ ("sync");
179 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
182 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
188 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
191 #ifndef MPC83xx_RESET
195 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
198 /* Interrupts and MMU off */
199 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
201 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
202 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
204 /* enable Reset Control Reg */
205 immap->reset.rpr = 0x52535445;
206 __asm__ __volatile__ ("sync");
207 __asm__ __volatile__ ("isync");
209 /* confirm Reset Control Reg is enabled */
210 while(!((immap->reset.rcer) & RCER_CRE));
212 printf("Resetting the board.");
217 /* perform reset, only one bit */
218 immap->reset.rcr = RCR_SWHR;
220 #else /* ! MPC83xx_RESET */
222 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
224 /* Interrupts and MMU off */
225 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
227 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
228 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
231 * Trying to execute the next instruction at a non-existing address
232 * should cause a machine check, resulting in reset
234 addr = CONFIG_SYS_RESET_ADDRESS;
236 printf("resetting the board.");
238 ((void (*)(void)) addr) ();
239 #endif /* MPC83xx_RESET */
246 * Get timebase clock frequency (like cpu_clk in Hz)
249 unsigned long get_tbclk(void)
253 tbclk = (gd->bus_clk + 3L) / 4L;
259 #if defined(CONFIG_WATCHDOG)
260 void watchdog_reset (void)
262 int re_enable = disable_interrupts();
264 /* Reset the 83xx watchdog */
265 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
266 immr->wdt.swsrr = 0x556c;
267 immr->wdt.swsrr = 0xaa39;
270 enable_interrupts ();
274 #if defined(CONFIG_DDR_ECC)
277 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
278 volatile dma83xx_t *dma = &immap->dma;
279 volatile u32 status = swab32(dma->dmasr0);
280 volatile u32 dmamr0 = swab32(dma->dmamr0);
284 /* initialize DMASARn, DMADAR and DMAABCRn */
285 dma->dmadar0 = (u32)0;
286 dma->dmasar0 = (u32)0;
289 __asm__ __volatile__ ("sync");
290 __asm__ __volatile__ ("isync");
293 dmamr0 &= ~DMA_CHANNEL_START;
294 dma->dmamr0 = swab32(dmamr0);
295 __asm__ __volatile__ ("sync");
296 __asm__ __volatile__ ("isync");
298 /* while the channel is busy, spin */
299 while(status & DMA_CHANNEL_BUSY) {
300 status = swab32(dma->dmasr0);
303 debug("DMA-init end\n");
308 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
309 volatile dma83xx_t *dma = &immap->dma;
310 volatile u32 status = swab32(dma->dmasr0);
311 volatile u32 byte_count = swab32(dma->dmabcr0);
313 /* while the channel is busy, spin */
314 while (status & DMA_CHANNEL_BUSY) {
315 status = swab32(dma->dmasr0);
318 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
319 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
325 int dma_xfer(void *dest, u32 count, void *src)
327 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
328 volatile dma83xx_t *dma = &immap->dma;
331 /* initialize DMASARn, DMADAR and DMAABCRn */
332 dma->dmadar0 = swab32((u32)dest);
333 dma->dmasar0 = swab32((u32)src);
334 dma->dmabcr0 = swab32(count);
336 __asm__ __volatile__ ("sync");
337 __asm__ __volatile__ ("isync");
339 /* init direct transfer, clear CS bit */
340 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
341 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
342 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
344 dma->dmamr0 = swab32(dmamr0);
346 __asm__ __volatile__ ("sync");
347 __asm__ __volatile__ ("isync");
349 /* set CS to start DMA transfer */
350 dmamr0 |= DMA_CHANNEL_START;
351 dma->dmamr0 = swab32(dmamr0);
352 __asm__ __volatile__ ("sync");
353 __asm__ __volatile__ ("isync");
355 return ((int)dma_check());
357 #endif /*CONFIG_DDR_ECC*/
360 * Initializes on-chip ethernet controllers.
361 * to override, implement board_eth_init()
363 int cpu_eth_init(bd_t *bis)
365 #if defined(CONFIG_UEC_ETH1)
368 #if defined(CONFIG_UEC_ETH2)
371 #if defined(CONFIG_UEC_ETH3)
374 #if defined(CONFIG_UEC_ETH4)
377 #if defined(CONFIG_UEC_ETH5)
380 #if defined(CONFIG_UEC_ETH6)
383 #if defined(CONFIG_TSEC_ENET)
384 tsec_standard_init(bis);