2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
40 volatile immap_t *immr;
41 ulong clock = gd->cpu_clk;
47 const struct cpu_type {
50 } cpu_type_list [] = {
58 CPU_TYPE_ENTRY(8347_TBGA_),
59 CPU_TYPE_ENTRY(8347_PBGA_),
61 CPU_TYPE_ENTRY(8358_TBGA_),
62 CPU_TYPE_ENTRY(8358_PBGA_),
69 immr = (immap_t *)CFG_IMMR;
73 switch (pvr & 0xffff0000) {
91 printf("Unknown core, ");
94 spridr = immr->sysconf.spridr;
96 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
97 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
99 puts(cpu_type_list[i].name);
100 if (IS_E_PROCESSOR(spridr))
102 if (REVID_MAJOR(spridr) >= 2)
104 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
105 REVID_MINOR(spridr));
109 if (i == ARRAY_SIZE(cpu_type_list))
110 printf("(SPRIDR %08x unknown), ", spridr);
112 printf(" at %s MHz, ", strmhz(buf, clock));
114 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
121 * Program a UPM with the code supplied in the table.
123 * The 'dummy' variable is used to increment the MAD. 'dummy' is
124 * supposed to be a pointer to the memory of the device being
125 * programmed by the UPM. The data in the MDR is written into
126 * memory and the MAD is incremented every time there's a read
127 * from 'dummy'. Unfortunately, the current prototype for this
128 * function doesn't allow for passing the address of this
129 * device, and changing the prototype will break a number lots
130 * of other code, so we need to use a round-about way of finding
131 * the value for 'dummy'.
133 * The value can be extracted from the base address bits of the
134 * Base Register (BR) associated with the specific UPM. To find
135 * that BR, we need to scan all 8 BRs until we find the one that
136 * has its MSEL bits matching the UPM we want. Once we know the
137 * right BR, we can extract the base address bits from it.
139 * The MxMR and the BR and OR of the chosen bank should all be
140 * configured before calling this function.
143 * upm: 0=UPMA, 1=UPMB, 2=UPMC
144 * table: Pointer to an array of values to program
145 * size: Number of elements in the array. Must be 64 or less.
147 void upmconfig (uint upm, uint *table, uint size)
149 #if defined(CONFIG_MPC834X)
150 volatile immap_t *immap = (immap_t *) CFG_IMMR;
151 volatile lbus83xx_t *lbus = &immap->lbus;
152 volatile uchar *dummy = NULL;
153 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
154 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
157 /* Scan all the banks to determine the base address of the device */
158 for (i = 0; i < 8; i++) {
159 if ((lbus->bank[i].br & BR_MSEL) == msel) {
160 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
166 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
170 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
171 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
173 for (i = 0; i < size; i++) {
174 lbus->mdr = table[i];
175 __asm__ __volatile__ ("sync");
176 *dummy; /* Write the value to memory and increment MAD */
177 __asm__ __volatile__ ("sync");
180 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
183 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
190 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
193 #ifndef MPC83xx_RESET
197 volatile immap_t *immap = (immap_t *) CFG_IMMR;
200 /* Interrupts and MMU off */
201 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
203 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
204 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
206 /* enable Reset Control Reg */
207 immap->reset.rpr = 0x52535445;
208 __asm__ __volatile__ ("sync");
209 __asm__ __volatile__ ("isync");
211 /* confirm Reset Control Reg is enabled */
212 while(!((immap->reset.rcer) & RCER_CRE));
214 printf("Resetting the board.");
219 /* perform reset, only one bit */
220 immap->reset.rcr = RCR_SWHR;
222 #else /* ! MPC83xx_RESET */
224 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
226 /* Interrupts and MMU off */
227 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
229 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
230 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
233 * Trying to execute the next instruction at a non-existing address
234 * should cause a machine check, resulting in reset
236 addr = CFG_RESET_ADDRESS;
238 printf("resetting the board.");
240 ((void (*)(void)) addr) ();
241 #endif /* MPC83xx_RESET */
248 * Get timebase clock frequency (like cpu_clk in Hz)
251 unsigned long get_tbclk(void)
255 tbclk = (gd->bus_clk + 3L) / 4L;
261 #if defined(CONFIG_WATCHDOG)
262 void watchdog_reset (void)
264 int re_enable = disable_interrupts();
266 /* Reset the 83xx watchdog */
267 volatile immap_t *immr = (immap_t *) CFG_IMMR;
268 immr->wdt.swsrr = 0x556c;
269 immr->wdt.swsrr = 0xaa39;
272 enable_interrupts ();
276 #if defined(CONFIG_DDR_ECC)
279 volatile immap_t *immap = (immap_t *)CFG_IMMR;
280 volatile dma83xx_t *dma = &immap->dma;
281 volatile u32 status = swab32(dma->dmasr0);
282 volatile u32 dmamr0 = swab32(dma->dmamr0);
286 /* initialize DMASARn, DMADAR and DMAABCRn */
287 dma->dmadar0 = (u32)0;
288 dma->dmasar0 = (u32)0;
291 __asm__ __volatile__ ("sync");
292 __asm__ __volatile__ ("isync");
295 dmamr0 &= ~DMA_CHANNEL_START;
296 dma->dmamr0 = swab32(dmamr0);
297 __asm__ __volatile__ ("sync");
298 __asm__ __volatile__ ("isync");
300 /* while the channel is busy, spin */
301 while(status & DMA_CHANNEL_BUSY) {
302 status = swab32(dma->dmasr0);
305 debug("DMA-init end\n");
310 volatile immap_t *immap = (immap_t *)CFG_IMMR;
311 volatile dma83xx_t *dma = &immap->dma;
312 volatile u32 status = swab32(dma->dmasr0);
313 volatile u32 byte_count = swab32(dma->dmabcr0);
315 /* while the channel is busy, spin */
316 while (status & DMA_CHANNEL_BUSY) {
317 status = swab32(dma->dmasr0);
320 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
321 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
327 int dma_xfer(void *dest, u32 count, void *src)
329 volatile immap_t *immap = (immap_t *)CFG_IMMR;
330 volatile dma83xx_t *dma = &immap->dma;
333 /* initialize DMASARn, DMADAR and DMAABCRn */
334 dma->dmadar0 = swab32((u32)dest);
335 dma->dmasar0 = swab32((u32)src);
336 dma->dmabcr0 = swab32(count);
338 __asm__ __volatile__ ("sync");
339 __asm__ __volatile__ ("isync");
341 /* init direct transfer, clear CS bit */
342 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
343 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
344 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
346 dma->dmamr0 = swab32(dmamr0);
348 __asm__ __volatile__ ("sync");
349 __asm__ __volatile__ ("isync");
351 /* set CS to start DMA transfer */
352 dmamr0 |= DMA_CHANNEL_START;
353 dma->dmamr0 = swab32(dmamr0);
354 __asm__ __volatile__ ("sync");
355 __asm__ __volatile__ ("isync");
357 return ((int)dma_check());
359 #endif /*CONFIG_DDR_ECC*/
361 #ifdef CONFIG_TSEC_ENET
362 /* Default initializations for TSEC controllers. To override,
363 * create a board-specific function called:
364 * int board_eth_init(bd_t *bis)
367 extern int tsec_initialize(bd_t * bis, int index, char *devname);
369 int cpu_eth_init(bd_t *bis)
371 #if defined(CONFIG_TSEC1)
372 tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
374 #if defined(CONFIG_TSEC2)
375 tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);