2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
32 #define CONFIG_8260 1 /* needed for Linux kernel header files */
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r14 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
70 GOT_ENTRY(__bss_start)
71 #if defined(CONFIG_HYMOD)
72 GOT_ENTRY(environment)
77 * Version string - must be in data segment because MPC8260 uses the first
78 * 256 bytes for the Hard Reset Configuration Word table (see below).
79 * Similarly, can't have the U-Boot Magic Number as the first thing in
80 * the image - don't know how this will affect the image tools, but I guess
87 .ascii " (", __DATE__, " - ", __TIME__, ")"
88 .ascii CONFIG_IDENT_STRING, "\0"
91 * Hard Reset Configuration Word (HRCW) table
93 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
94 * such as whether there is an external memory controller, whether the
95 * PowerPC core is disabled (i.e. only the communications processor is
96 * active, accessed by another CPU on the bus), whether using external
97 * arbitration, external bus mode, boot port size, core initial prefix,
98 * internal space base, boot memory space, etc.
100 * These things dictate where the processor begins execution, where the
101 * boot ROM appears in memory, the memory controller setup when access
102 * boot ROM, etc. The HRCW is *extremely* important.
104 * The HRCW is read from the bus during reset. One CPU on the bus will
105 * be a hard reset configuration master, any others will be hard reset
106 * configuration slaves. The master reads eight HRCWs from flash during
107 * reset - the first it uses for itself, the other 7 it communicates to
108 * up to 7 configuration slaves by some complicated mechanism, which is
109 * not really important here.
111 * The configuration master performs 32 successive reads starting at address
112 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
113 * bits is read, and always from byte lane D[0-7] (so that port size of the
114 * boot device does not matter). The first four reads form the 32 bit HRCW
115 * for the master itself. The second four reads form the HRCW for the first
116 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
117 * concatenating the four bytes, with the first read placed in byte 0 (the
118 * most significant byte), and so on with the fourth read placed in byte 3
119 * (the least significant byte).
121 #define _HRCW_TABLE_ENTRY(w) \
122 .fill 8,1,(((w)>>24)&0xff); \
123 .fill 8,1,(((w)>>16)&0xff); \
124 .fill 8,1,(((w)>> 8)&0xff); \
125 .fill 8,1,(((w) )&0xff)
129 _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
130 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
131 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
132 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
133 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
134 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
135 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
136 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
138 * After configuration, a system reset exception is executed using the
139 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
140 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
141 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
142 * of MSR[IP] is determined by the CIP field in the HRCW.
144 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
145 * This determines the location of the boot ROM (flash or EPROM) in the
146 * processor's address space at boot time. As long as the HRCW is set up
147 * so that we eventually end up executing the code below when the processor
148 * executes the reset exception, the actual values used should not matter.
150 * Once we have got here, the address mask in OR0 is cleared so that the
151 * bottom 32K of the boot ROM is effectively repeated all throughout the
152 * processor's address space, after which we can jump to the absolute
153 * address at which the boot ROM was linked at compile time, and proceed
154 * to initialise the memory controller without worrying if the rug will be
155 * pulled out from under us, so to speak (it will be fine as long as we
156 * configure BR0 with the same boot ROM link address).
158 . = EXC_OFF_SYS_RESET
162 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
165 . = EXC_OFF_SYS_RESET + 0x10
169 li r21, BOOTFLAG_WARM /* Software reboot */
174 mfmsr r5 /* save msr contents */
176 #if defined(CONFIG_COGENT)
177 /* this is what the cogent EPROM does */
182 #endif /* CONFIG_COGENT */
184 #if defined(CFG_DEFAULT_IMMR)
186 ori r3, r3, CFG_IMMR@l
187 lis r4, CFG_DEFAULT_IMMR@h
189 #endif /* CFG_DEFAULT_IMMR */
191 /* Initialise the MPC8260 processor core */
192 /*--------------------------------------------------------------*/
197 /* When booting from ROM (Flash or EPROM), clear the */
198 /* Address Mask in OR0 so ROM appears everywhere */
199 /*--------------------------------------------------------------*/
201 lis r3, (CFG_IMMR+IM_REGBASE)@h
207 /* Calculate absolute address in FLASH and jump there */
208 /*--------------------------------------------------------------*/
210 lis r3, CFG_MONITOR_BASE@h
211 ori r3, r3, CFG_MONITOR_BASE@l
212 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
217 #endif /* CFG_RAMBOOT */
219 /* initialize some things that are hard to access from C */
220 /*--------------------------------------------------------------*/
222 lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */
223 ori r1, r3, CFG_INIT_SP_OFFSET
224 li r0, 0 /* Make room for stack frame header and */
225 stwu r0, -4(r1) /* clear final stack frame so that */
226 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
228 /* let the C-code set up the rest */
230 /* Be careful to keep code relocatable ! */
231 /*--------------------------------------------------------------*/
233 GET_GOT /* initialize GOT access */
236 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
239 bl init_debug /* set up debugging stuff */
244 bl board_init_f /* run 1st part of board init code (in Flash)*/
250 .globl _start_of_vectors
254 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
256 /* Data Storage exception. */
257 STD_EXCEPTION(0x300, DataStorage, UnknownException)
259 /* Instruction Storage exception. */
260 STD_EXCEPTION(0x400, InstStorage, UnknownException)
262 /* External Interrupt exception. */
263 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
265 /* Alignment exception. */
273 addi r3,r1,STACK_FRAME_OVERHEAD
275 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
276 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
277 lwz r6,GOT(transfer_to_handler)
281 .long AlignmentException - _start + EXC_OFF_SYS_RESET
282 .long int_return - _start + EXC_OFF_SYS_RESET
284 /* Program check exception */
288 addi r3,r1,STACK_FRAME_OVERHEAD
290 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
291 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
292 lwz r6,GOT(transfer_to_handler)
296 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
297 .long int_return - _start + EXC_OFF_SYS_RESET
299 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
301 /* I guess we could implement decrementer, and may have
302 * to someday for timekeeping.
304 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
306 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
307 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
311 * r0 - SYSCALL number
315 addis r11,r0,0 /* get functions table addr */
316 ori r11,r11,0 /* Note: this code is patched in trap_init */
317 addis r12,r0,0 /* get number of functions */
323 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
327 li r20,0xd00-4 /* Get stack pointer */
329 subi r12,r12,12 /* Adjust stack pointer */
330 li r0,0xc00+_end_back-SystemCall
331 cmplw 0, r0, r12 /* Check stack overflow */
342 li r12,0xc00+_back-SystemCall
351 mfmsr r11 /* Disable interrupts */
355 SYNC /* Some chip revs need this... */
359 li r12,0xd00-4 /* restore regs */
369 addi r12,r12,12 /* Adjust stack pointer */
377 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
379 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
380 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
382 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
383 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
384 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
388 * This exception occurs when the program counter matches the
389 * Instruction Address Breakpoint Register (IABR).
391 * I want the cpu to halt if this occurs so I can hunt around
392 * with the debugger and look at things.
394 * When DEBUG is defined, both machine check enable (in the MSR)
395 * and checkstop reset enable (in the reset mode register) are
396 * turned off and so a checkstop condition will result in the cpu
399 * I force the cpu into a checkstop condition by putting an illegal
400 * instruction here (at least this is the theory).
402 * well - that didnt work, so just do an infinite loop!
406 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
408 STD_EXCEPTION(0x1400, SMI, UnknownException)
410 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
411 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
412 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
413 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
414 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
415 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
416 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
417 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
418 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
419 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
420 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
421 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
422 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
423 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
424 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
425 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
426 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
427 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
428 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
429 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
430 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
431 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
432 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
433 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
434 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
435 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
436 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
439 .globl _end_of_vectors
445 * This code finishes saving the registers to the exception frame
446 * and jumps to the appropriate handler for the exception.
447 * Register r21 is pointer into trap frame, r1 has new stack pointer.
449 .globl transfer_to_handler
460 andi. r24,r23,0x3f00 /* get vector offset */
464 lwz r24,0(r23) /* virtual address of handler */
465 lwz r23,4(r23) /* where to go when done */
470 rfi /* jump to handler, enable MMU */
473 mfmsr r28 /* Disable interrupts */
477 SYNC /* Some chip revs need this... */
492 lwz r2,_NIP(r1) /* Restore environment */
502 #if defined(CONFIG_COGENT)
505 * This code initialises the MPC8260 processor core
506 * (conforms to PowerPC 603e spec)
509 .globl cogent_init_8260
512 /* Taken from page 14 of CMA282 manual */
513 /*--------------------------------------------------------------*/
515 lis r4, (CFG_IMMR+IM_REGBASE)@h
517 stw r3, IM_IMMR@l(r4)
518 lwz r3, IM_IMMR@l(r4)
521 ori r3, r3, CFG_SYPCR@l
522 stw r3, IM_SYPCR@l(r4)
523 lwz r3, IM_SYPCR@l(r4)
526 ori r3, r3, CFG_SCCR@l
527 stw r3, IM_SCCR@l(r4)
528 lwz r3, IM_SCCR@l(r4)
531 /* the rest of this was disassembled from the */
532 /* EPROM code that came with my CMA282 CPU module */
533 /*--------------------------------------------------------------*/
547 /*--------------------------------------------------------------*/
551 #endif /* CONFIG_COGENT */
554 * This code initialises the MPC8260 processor core
555 * (conforms to PowerPC 603e spec)
556 * Note: expects original MSR contents to be in r5.
559 .globl init_8260_core
562 /* Initialize machine status; enable machine check interrupt */
563 /*--------------------------------------------------------------*/
565 li r3, MSR_KERNEL /* Set ME and RI flags */
566 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
568 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
570 SYNC /* Some chip revs need this... */
573 mtspr SRR1, r3 /* Make SRR1 match MSR */
575 /* Initialise the SYPCR early, and reset the watchdog (if req) */
576 /*--------------------------------------------------------------*/
578 lis r3, (CFG_IMMR+IM_REGBASE)@h
579 #if !defined(CONFIG_COGENT)
581 ori r4, r4, CFG_SYPCR@l
582 stw r4, IM_SYPCR@l(r3)
583 #endif /* !CONFIG_COGENT */
584 #if defined(CONFIG_WATCHDOG)
585 li r4, 21868 /* = 0x556c */
586 sth r4, IM_SWSR@l(r3)
587 li r4, -21959 /* = 0xaa39 */
588 sth r4, IM_SWSR@l(r3)
589 #endif /* CONFIG_WATCHDOG */
591 /* Initialize the Hardware Implementation-dependent Registers */
592 /* HID0 also contains cache control */
593 /*--------------------------------------------------------------*/
595 lis r3, CFG_HID0_INIT@h
596 ori r3, r3, CFG_HID0_INIT@l
600 lis r3, CFG_HID0_FINAL@h
601 ori r3, r3, CFG_HID0_FINAL@l
606 ori r3, r3, CFG_HID2@l
609 /* clear all BAT's */
610 /*--------------------------------------------------------------*/
631 /* invalidate all tlb's */
633 /* From the 603e User Manual: "The 603e provides the ability to */
634 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
635 /* instruction invalidates the TLB entry indexed by the EA, and */
636 /* operates on both the instruction and data TLBs simultaneously*/
637 /* invalidating four TLB entries (both sets in each TLB). The */
638 /* index corresponds to bits 15-19 of the EA. To invalidate all */
639 /* entries within both TLBs, 32 tlbie instructions should be */
640 /* issued, incrementing this field by one each time." */
642 /* "Note that the tlbia instruction is not implemented on the */
645 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
646 /* incrementing by 0x1000 each time. The code below is sort of */
647 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
649 /*--------------------------------------------------------------*/
660 /*--------------------------------------------------------------*/
667 * initialise things related to debugging.
669 * must be called after the global offset table (GOT) is initialised
670 * (GET_GOT) and after cpu_init_f() has executed.
676 lis r3, (CFG_IMMR+IM_REGBASE)@h
678 /* Quick and dirty hack to enable the RAM and copy the */
679 /* vectors so that we can take exceptions. */
680 /*--------------------------------------------------------------*/
681 /* write Memory Refresh Prescaler */
683 sth r4, IM_MPTPR@l(r3)
684 /* write 60x Refresh Timer */
686 stb r4, IM_PSRT@l(r3)
687 /* init the 60x SDRAM Mode Register */
688 lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h
689 ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l
690 stw r4, IM_PSDMR@l(r3)
691 /* write Precharge All Banks command */
692 lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h
693 ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l
694 stw r4, IM_PSDMR@l(r3)
696 /* write eight CBR Refresh commands */
697 lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h
698 ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l
699 stw r4, IM_PSDMR@l(r3)
708 /* write Mode Register Write command */
709 lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h
710 ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l
711 stw r4, IM_PSDMR@l(r3)
713 /* write Normal Operation command and enable Refresh */
714 lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
715 ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
716 stw r4, IM_PSDMR@l(r3)
718 /* RAM should now be operational */
720 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
722 lwz r3, GOT(_end_of_vectors)
723 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
724 lis r5, VEC_WRD_CNT@h
725 ori r5, r5, VEC_WRD_CNT@l
732 /* Load the Instruction Address Breakpoint Register (IABR). */
734 /* The address to load is stored in the first word of dual port */
735 /* ram and should be preserved while the power is on, so you */
736 /* can plug addresses into that location then reset the cpu and */
737 /* this code will load that address into the IABR after the */
740 /* When the program counter matches the contents of the IABR, */
741 /* an exception is generated (before the instruction at that */
742 /* location completes). The vector for this exception is 0x1300 */
743 /*--------------------------------------------------------------*/
748 /* Set the entire dual port RAM (where the initial stack */
749 /* resides) to a known value - makes it easier to see where */
750 /* the stack has been written */
751 /*--------------------------------------------------------------*/
752 lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h
753 ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l
754 li r4, ((CFG_INIT_SP_OFFSET - 4) / 4)
757 ori r4, r4, 0xdeadbeaf@l
763 /*--------------------------------------------------------------*/
770 * Note: requires that all cache bits in
771 * HID0 are in the low half word.
778 ori r4, r4, HID0_ILOCK
780 ori r4, r3, HID0_ICFI
782 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
784 mtspr HID0, r3 /* clears invalidate */
787 .globl icache_disable
791 ori r4, r4, HID0_ICE|HID0_ILOCK
793 ori r4, r3, HID0_ICFI
795 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
797 mtspr HID0, r3 /* clears invalidate */
803 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
811 ori r4, r4, HID0_DLOCK
815 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
817 mtspr HID0, r3 /* clears invalidate */
820 .globl dcache_disable
824 ori r4, r4, HID0_DCE|HID0_DLOCK
828 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
830 mtspr HID0, r3 /* clears invalidate */
836 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
844 /*------------------------------------------------------------------------------*/
847 * void relocate_code (addr_sp, gd, addr_moni)
849 * This "function" does not return, instead it continues in RAM
850 * after relocating the monitor code.
854 * r5 = length in bytes
859 mr r1, r3 /* Set new stack pointer */
860 mr r9, r4 /* Save copy of Global Data pointer */
861 mr r10, r5 /* Save copy of Destination Address */
863 mr r3, r5 /* Destination Address */
864 lis r4, CFG_MONITOR_BASE@h /* Source Address */
865 ori r4, r4, CFG_MONITOR_BASE@l
866 lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
867 ori r5, r5, CFG_MONITOR_LEN@l
868 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
873 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
879 /* First our own GOT */
881 /* then the one used by the C code */
891 beq cr1,4f /* In place copy is not necessary */
892 beq 7f /* Protect against 0 count */
911 * Now flush the cache: note that we must start from a cache aligned
912 * address. Otherwise we might miss one cache line.
916 beq 7f /* Always flush prefetch queue in any case */
919 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
920 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
928 sync /* Wait for all dcbst to complete on bus */
929 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
930 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
938 7: sync /* Wait for all icbi to complete on bus */
942 * We are done. Do not return, instead branch to second part of board
943 * initialization, now running from RAM.
946 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
953 * Relocation Function, r14 point to got2+0x8000
955 * Adjust got2 pointers, no need to check for 0, this code
956 * already puts a few entries in the table.
958 li r0,__got2_entries@sectoff@l
959 la r3,GOT(_GOT2_TABLE_)
960 lwz r11,GOT(_GOT2_TABLE_)
970 * Now adjust the fixups and the pointers to the fixups
971 * in case we need to move ourselves again.
973 2: li r0,__fixup_entries@sectoff@l
974 lwz r3,GOT(_FIXUP_TABLE_)
988 * Now clear BSS segment
990 lwz r3,GOT(__bss_start)
991 #if defined(CONFIG_HYMOD)
993 * For HYMOD - the environment is the very last item in flash.
994 * The real .bss stops just before environment starts, so only
995 * clear up to that point.
997 * taken from mods for FADS board
999 lwz r4,GOT(environment)
1015 mr r3, r9 /* Global Data pointer */
1016 mr r4, r10 /* Destination Address */
1019 /* Problems accessing "end" in C, so do it here */
1026 * Copy exception vector code to low memory
1029 * r7: source address, r8: end address, r9: target address
1034 lwz r8, GOT(_end_of_vectors)
1036 rlwinm r9, r7, 0, 18, 31 /* _start & 0x3FFF */
1039 bgelr /* return if r7>=r8 - just in case */
1041 mflr r4 /* save link register */
1051 * relocate `hdlr' and `int_return' entries
1053 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1054 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1057 addi r7, r7, 0x100 /* next exception vector */
1061 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1064 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1067 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1068 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1071 addi r7, r7, 0x100 /* next exception vector */
1075 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1076 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1079 addi r7, r7, 0x100 /* next exception vector */
1083 mfmsr r3 /* now that the vectors have */
1084 lis r7, MSR_IP@h /* relocated into low memory */
1085 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1086 andc r3, r3, r7 /* (if it was on) */
1087 SYNC /* Some chip revs need this... */
1091 mtlr r4 /* restore link register */
1095 * Function: relocate entries for one exception vector
1098 lwz r0, 0(r7) /* hdlr ... */
1099 add r0, r0, r3 /* ... += dest_addr */
1102 lwz r0, 4(r7) /* int_return ... */
1103 add r0, r0, r3 /* ... += dest_addr */