2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
32 #define CONFIG_8260 1 /* needed for Linux kernel header files */
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r14 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
71 GOT_ENTRY(__bss_start)
72 #if defined(CONFIG_HYMOD)
73 GOT_ENTRY(environment)
78 * Version string - must be in data segment because MPC8260 uses the first
79 * 256 bytes for the Hard Reset Configuration Word table (see below).
80 * Similarly, can't have the U-Boot Magic Number as the first thing in
81 * the image - don't know how this will affect the image tools, but I guess
88 .ascii " (", __DATE__, " - ", __TIME__, ")"
89 .ascii CONFIG_IDENT_STRING, "\0"
92 * Hard Reset Configuration Word (HRCW) table
94 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
95 * such as whether there is an external memory controller, whether the
96 * PowerPC core is disabled (i.e. only the communications processor is
97 * active, accessed by another CPU on the bus), whether using external
98 * arbitration, external bus mode, boot port size, core initial prefix,
99 * internal space base, boot memory space, etc.
101 * These things dictate where the processor begins execution, where the
102 * boot ROM appears in memory, the memory controller setup when access
103 * boot ROM, etc. The HRCW is *extremely* important.
105 * The HRCW is read from the bus during reset. One CPU on the bus will
106 * be a hard reset configuration master, any others will be hard reset
107 * configuration slaves. The master reads eight HRCWs from flash during
108 * reset - the first it uses for itself, the other 7 it communicates to
109 * up to 7 configuration slaves by some complicated mechanism, which is
110 * not really important here.
112 * The configuration master performs 32 successive reads starting at address
113 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
114 * bits is read, and always from byte lane D[0-7] (so that port size of the
115 * boot device does not matter). The first four reads form the 32 bit HRCW
116 * for the master itself. The second four reads form the HRCW for the first
117 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
118 * concatenating the four bytes, with the first read placed in byte 0 (the
119 * most significant byte), and so on with the fourth read placed in byte 3
120 * (the least significant byte).
122 #define _HRCW_TABLE_ENTRY(w) \
123 .fill 8,1,(((w)>>24)&0xff); \
124 .fill 8,1,(((w)>>16)&0xff); \
125 .fill 8,1,(((w)>> 8)&0xff); \
126 .fill 8,1,(((w) )&0xff)
130 _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
131 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
132 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
133 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
134 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
135 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
136 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
137 _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
139 * After configuration, a system reset exception is executed using the
140 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
141 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
142 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
143 * of MSR[IP] is determined by the CIP field in the HRCW.
145 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
146 * This determines the location of the boot ROM (flash or EPROM) in the
147 * processor's address space at boot time. As long as the HRCW is set up
148 * so that we eventually end up executing the code below when the processor
149 * executes the reset exception, the actual values used should not matter.
151 * Once we have got here, the address mask in OR0 is cleared so that the
152 * bottom 32K of the boot ROM is effectively repeated all throughout the
153 * processor's address space, after which we can jump to the absolute
154 * address at which the boot ROM was linked at compile time, and proceed
155 * to initialise the memory controller without worrying if the rug will be
156 * pulled out from under us, so to speak (it will be fine as long as we
157 * configure BR0 with the same boot ROM link address).
159 . = EXC_OFF_SYS_RESET
163 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
167 . = EXC_OFF_SYS_RESET + 0x10
171 li r21, BOOTFLAG_WARM /* Software reboot */
175 #if defined(CONFIG_MPC8260ADS)
176 lis r3, CFG_DEFAULT_IMMR@h
180 rlwinm r4, r4, 0, 8, 5
186 #endif /* CONFIG_MPC8260ADS */
188 mfmsr r5 /* save msr contents */
190 #if defined(CONFIG_COGENT)
191 /* this is what the cogent EPROM does */
196 #endif /* CONFIG_COGENT */
198 #if defined(CFG_DEFAULT_IMMR)
200 ori r3, r3, CFG_IMMR@l
201 lis r4, CFG_DEFAULT_IMMR@h
203 #endif /* CFG_DEFAULT_IMMR */
205 /* Initialise the MPC8260 processor core */
206 /*--------------------------------------------------------------*/
211 /* When booting from ROM (Flash or EPROM), clear the */
212 /* Address Mask in OR0 so ROM appears everywhere */
213 /*--------------------------------------------------------------*/
215 lis r3, (CFG_IMMR+IM_REGBASE)@h
221 /* Calculate absolute address in FLASH and jump there */
222 /*--------------------------------------------------------------*/
224 lis r3, CFG_MONITOR_BASE@h
225 ori r3, r3, CFG_MONITOR_BASE@l
226 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
231 #endif /* CFG_RAMBOOT */
233 /* initialize some things that are hard to access from C */
234 /*--------------------------------------------------------------*/
236 lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */
237 ori r1, r3, CFG_INIT_SP_OFFSET
238 li r0, 0 /* Make room for stack frame header and */
239 stwu r0, -4(r1) /* clear final stack frame so that */
240 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
242 /* let the C-code set up the rest */
244 /* Be careful to keep code relocatable ! */
245 /*--------------------------------------------------------------*/
247 GET_GOT /* initialize GOT access */
250 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
253 bl init_debug /* set up debugging stuff */
258 bl board_init_f /* run 1st part of board init code (in Flash)*/
264 .globl _start_of_vectors
268 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
270 /* Data Storage exception. */
271 STD_EXCEPTION(0x300, DataStorage, UnknownException)
273 /* Instruction Storage exception. */
274 STD_EXCEPTION(0x400, InstStorage, UnknownException)
276 /* External Interrupt exception. */
277 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
279 /* Alignment exception. */
287 addi r3,r1,STACK_FRAME_OVERHEAD
289 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
290 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
291 lwz r6,GOT(transfer_to_handler)
295 .long AlignmentException - _start + EXC_OFF_SYS_RESET
296 .long int_return - _start + EXC_OFF_SYS_RESET
298 /* Program check exception */
302 addi r3,r1,STACK_FRAME_OVERHEAD
304 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
305 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
306 lwz r6,GOT(transfer_to_handler)
310 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
311 .long int_return - _start + EXC_OFF_SYS_RESET
313 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
315 /* I guess we could implement decrementer, and may have
316 * to someday for timekeeping.
318 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
320 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
321 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
325 * r0 - SYSCALL number
329 addis r11,r0,0 /* get functions table addr */
330 ori r11,r11,0 /* Note: this code is patched in trap_init */
331 addis r12,r0,0 /* get number of functions */
337 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
341 li r20,0xd00-4 /* Get stack pointer */
343 subi r12,r12,12 /* Adjust stack pointer */
344 li r0,0xc00+_end_back-SystemCall
345 cmplw 0, r0, r12 /* Check stack overflow */
356 li r12,0xc00+_back-SystemCall
365 mfmsr r11 /* Disable interrupts */
369 SYNC /* Some chip revs need this... */
373 li r12,0xd00-4 /* restore regs */
383 addi r12,r12,12 /* Adjust stack pointer */
391 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
393 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
394 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
396 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
397 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
398 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
402 * This exception occurs when the program counter matches the
403 * Instruction Address Breakpoint Register (IABR).
405 * I want the cpu to halt if this occurs so I can hunt around
406 * with the debugger and look at things.
408 * When DEBUG is defined, both machine check enable (in the MSR)
409 * and checkstop reset enable (in the reset mode register) are
410 * turned off and so a checkstop condition will result in the cpu
413 * I force the cpu into a checkstop condition by putting an illegal
414 * instruction here (at least this is the theory).
416 * well - that didnt work, so just do an infinite loop!
420 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
422 STD_EXCEPTION(0x1400, SMI, UnknownException)
424 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
425 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
426 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
427 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
428 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
429 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
430 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
431 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
432 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
433 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
434 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
435 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
436 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
437 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
438 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
439 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
440 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
441 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
442 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
443 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
444 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
445 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
446 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
447 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
448 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
449 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
450 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
453 .globl _end_of_vectors
459 * This code finishes saving the registers to the exception frame
460 * and jumps to the appropriate handler for the exception.
461 * Register r21 is pointer into trap frame, r1 has new stack pointer.
463 .globl transfer_to_handler
474 andi. r24,r23,0x3f00 /* get vector offset */
478 lwz r24,0(r23) /* virtual address of handler */
479 lwz r23,4(r23) /* where to go when done */
484 rfi /* jump to handler, enable MMU */
487 mfmsr r28 /* Disable interrupts */
491 SYNC /* Some chip revs need this... */
506 lwz r2,_NIP(r1) /* Restore environment */
516 #if defined(CONFIG_COGENT)
519 * This code initialises the MPC8260 processor core
520 * (conforms to PowerPC 603e spec)
523 .globl cogent_init_8260
526 /* Taken from page 14 of CMA282 manual */
527 /*--------------------------------------------------------------*/
529 lis r4, (CFG_IMMR+IM_REGBASE)@h
531 stw r3, IM_IMMR@l(r4)
532 lwz r3, IM_IMMR@l(r4)
535 ori r3, r3, CFG_SYPCR@l
536 stw r3, IM_SYPCR@l(r4)
537 lwz r3, IM_SYPCR@l(r4)
540 ori r3, r3, CFG_SCCR@l
541 stw r3, IM_SCCR@l(r4)
542 lwz r3, IM_SCCR@l(r4)
545 /* the rest of this was disassembled from the */
546 /* EPROM code that came with my CMA282 CPU module */
547 /*--------------------------------------------------------------*/
561 /*--------------------------------------------------------------*/
565 #endif /* CONFIG_COGENT */
568 * This code initialises the MPC8260 processor core
569 * (conforms to PowerPC 603e spec)
570 * Note: expects original MSR contents to be in r5.
573 .globl init_8260_core
576 /* Initialize machine status; enable machine check interrupt */
577 /*--------------------------------------------------------------*/
579 li r3, MSR_KERNEL /* Set ME and RI flags */
580 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
582 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
584 SYNC /* Some chip revs need this... */
587 mtspr SRR1, r3 /* Make SRR1 match MSR */
589 /* Initialise the SYPCR early, and reset the watchdog (if req) */
590 /*--------------------------------------------------------------*/
592 lis r3, (CFG_IMMR+IM_REGBASE)@h
593 #if !defined(CONFIG_COGENT)
595 ori r4, r4, CFG_SYPCR@l
596 stw r4, IM_SYPCR@l(r3)
597 #endif /* !CONFIG_COGENT */
598 #if defined(CONFIG_WATCHDOG)
599 li r4, 21868 /* = 0x556c */
600 sth r4, IM_SWSR@l(r3)
601 li r4, -21959 /* = 0xaa39 */
602 sth r4, IM_SWSR@l(r3)
603 #endif /* CONFIG_WATCHDOG */
605 /* Initialize the Hardware Implementation-dependent Registers */
606 /* HID0 also contains cache control */
607 /*--------------------------------------------------------------*/
609 lis r3, CFG_HID0_INIT@h
610 ori r3, r3, CFG_HID0_INIT@l
614 lis r3, CFG_HID0_FINAL@h
615 ori r3, r3, CFG_HID0_FINAL@l
620 ori r3, r3, CFG_HID2@l
623 /* clear all BAT's */
624 /*--------------------------------------------------------------*/
645 /* invalidate all tlb's */
647 /* From the 603e User Manual: "The 603e provides the ability to */
648 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
649 /* instruction invalidates the TLB entry indexed by the EA, and */
650 /* operates on both the instruction and data TLBs simultaneously*/
651 /* invalidating four TLB entries (both sets in each TLB). The */
652 /* index corresponds to bits 15-19 of the EA. To invalidate all */
653 /* entries within both TLBs, 32 tlbie instructions should be */
654 /* issued, incrementing this field by one each time." */
656 /* "Note that the tlbia instruction is not implemented on the */
659 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
660 /* incrementing by 0x1000 each time. The code below is sort of */
661 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
663 /*--------------------------------------------------------------*/
674 /*--------------------------------------------------------------*/
681 * initialise things related to debugging.
683 * must be called after the global offset table (GOT) is initialised
684 * (GET_GOT) and after cpu_init_f() has executed.
690 lis r3, (CFG_IMMR+IM_REGBASE)@h
692 /* Quick and dirty hack to enable the RAM and copy the */
693 /* vectors so that we can take exceptions. */
694 /*--------------------------------------------------------------*/
695 /* write Memory Refresh Prescaler */
697 sth r4, IM_MPTPR@l(r3)
698 /* write 60x Refresh Timer */
700 stb r4, IM_PSRT@l(r3)
701 /* init the 60x SDRAM Mode Register */
702 lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h
703 ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l
704 stw r4, IM_PSDMR@l(r3)
705 /* write Precharge All Banks command */
706 lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h
707 ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l
708 stw r4, IM_PSDMR@l(r3)
710 /* write eight CBR Refresh commands */
711 lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h
712 ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l
713 stw r4, IM_PSDMR@l(r3)
722 /* write Mode Register Write command */
723 lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h
724 ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l
725 stw r4, IM_PSDMR@l(r3)
727 /* write Normal Operation command and enable Refresh */
728 lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
729 ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
730 stw r4, IM_PSDMR@l(r3)
732 /* RAM should now be operational */
734 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
736 lwz r3, GOT(_end_of_vectors)
737 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
738 lis r5, VEC_WRD_CNT@h
739 ori r5, r5, VEC_WRD_CNT@l
746 /* Load the Instruction Address Breakpoint Register (IABR). */
748 /* The address to load is stored in the first word of dual port */
749 /* ram and should be preserved while the power is on, so you */
750 /* can plug addresses into that location then reset the cpu and */
751 /* this code will load that address into the IABR after the */
754 /* When the program counter matches the contents of the IABR, */
755 /* an exception is generated (before the instruction at that */
756 /* location completes). The vector for this exception is 0x1300 */
757 /*--------------------------------------------------------------*/
762 /* Set the entire dual port RAM (where the initial stack */
763 /* resides) to a known value - makes it easier to see where */
764 /* the stack has been written */
765 /*--------------------------------------------------------------*/
766 lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h
767 ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l
768 li r4, ((CFG_INIT_SP_OFFSET - 4) / 4)
771 ori r4, r4, 0xdeadbeaf@l
777 /*--------------------------------------------------------------*/
784 * Note: requires that all cache bits in
785 * HID0 are in the low half word.
792 ori r4, r4, HID0_ILOCK
794 ori r4, r3, HID0_ICFI
796 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
798 mtspr HID0, r3 /* clears invalidate */
801 .globl icache_disable
805 ori r4, r4, HID0_ICE|HID0_ILOCK
807 ori r4, r3, HID0_ICFI
809 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
811 mtspr HID0, r3 /* clears invalidate */
817 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
825 ori r4, r4, HID0_DLOCK
829 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
831 mtspr HID0, r3 /* clears invalidate */
834 .globl dcache_disable
838 ori r4, r4, HID0_DCE|HID0_DLOCK
842 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
844 mtspr HID0, r3 /* clears invalidate */
850 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
858 /*------------------------------------------------------------------------------*/
861 * void relocate_code (addr_sp, gd, addr_moni)
863 * This "function" does not return, instead it continues in RAM
864 * after relocating the monitor code.
868 * r5 = length in bytes
873 mr r1, r3 /* Set new stack pointer */
874 mr r9, r4 /* Save copy of Global Data pointer */
875 mr r10, r5 /* Save copy of Destination Address */
877 mr r3, r5 /* Destination Address */
878 lis r4, CFG_MONITOR_BASE@h /* Source Address */
879 ori r4, r4, CFG_MONITOR_BASE@l
880 lwz r5, GOT(__init_end)
882 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
887 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
893 /* First our own GOT */
895 /* then the one used by the C code */
905 beq cr1,4f /* In place copy is not necessary */
906 beq 7f /* Protect against 0 count */
925 * Now flush the cache: note that we must start from a cache aligned
926 * address. Otherwise we might miss one cache line.
930 beq 7f /* Always flush prefetch queue in any case */
933 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
934 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
942 sync /* Wait for all dcbst to complete on bus */
943 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
944 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
952 7: sync /* Wait for all icbi to complete on bus */
956 * We are done. Do not return, instead branch to second part of board
957 * initialization, now running from RAM.
960 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
967 * Relocation Function, r14 point to got2+0x8000
969 * Adjust got2 pointers, no need to check for 0, this code
970 * already puts a few entries in the table.
972 li r0,__got2_entries@sectoff@l
973 la r3,GOT(_GOT2_TABLE_)
974 lwz r11,GOT(_GOT2_TABLE_)
984 * Now adjust the fixups and the pointers to the fixups
985 * in case we need to move ourselves again.
987 2: li r0,__fixup_entries@sectoff@l
988 lwz r3,GOT(_FIXUP_TABLE_)
1002 * Now clear BSS segment
1004 lwz r3,GOT(__bss_start)
1005 #if defined(CONFIG_HYMOD)
1007 * For HYMOD - the environment is the very last item in flash.
1008 * The real .bss stops just before environment starts, so only
1009 * clear up to that point.
1011 * taken from mods for FADS board
1013 lwz r4,GOT(environment)
1029 mr r3, r9 /* Global Data pointer */
1030 mr r4, r10 /* Destination Address */
1034 * Copy exception vector code to low memory
1037 * r7: source address, r8: end address, r9: target address
1042 lwz r8, GOT(_end_of_vectors)
1044 li r9, 0x100 /* reset vector always at 0x100 */
1047 bgelr /* return if r7>=r8 - just in case */
1049 mflr r4 /* save link register */
1059 * relocate `hdlr' and `int_return' entries
1061 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1062 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1065 addi r7, r7, 0x100 /* next exception vector */
1069 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1072 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1075 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1076 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1079 addi r7, r7, 0x100 /* next exception vector */
1083 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1084 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1087 addi r7, r7, 0x100 /* next exception vector */
1091 mfmsr r3 /* now that the vectors have */
1092 lis r7, MSR_IP@h /* relocated into low memory */
1093 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1094 andc r3, r3, r7 /* (if it was on) */
1095 SYNC /* Some chip revs need this... */
1099 mtlr r4 /* restore link register */
1103 * Function: relocate entries for one exception vector
1106 lwz r0, 0(r7) /* hdlr ... */
1107 add r0, r0, r3 /* ... += dest_addr */
1110 lwz r0, 4(r7) /* int_return ... */
1111 add r0, r0, r3 /* ... += dest_addr */