2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
30 #include <timestamp.h>
33 #define CONFIG_8260 1 /* needed for Linux kernel header files */
34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
36 #include <ppc_asm.tmpl>
39 #include <asm/cache.h>
42 #ifndef CONFIG_IDENT_STRING
43 #define CONFIG_IDENT_STRING ""
46 /* We don't want the MMU yet.
49 /* Floating Point enable, Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL (MSR_FP|MSR_RI)
53 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
57 * Set up GOT: Global Offset Table
59 * Use r14 to access the GOT
62 GOT_ENTRY(_GOT2_TABLE_)
63 GOT_ENTRY(_FIXUP_TABLE_)
66 GOT_ENTRY(_start_of_vectors)
67 GOT_ENTRY(_end_of_vectors)
68 GOT_ENTRY(transfer_to_handler)
72 GOT_ENTRY(__bss_start)
73 #if defined(CONFIG_HYMOD)
74 GOT_ENTRY(environment)
79 * Version string - must be in data segment because MPC8260 uses the first
80 * 256 bytes for the Hard Reset Configuration Word table (see below).
81 * Similarly, can't have the U-Boot Magic Number as the first thing in
82 * the image - don't know how this will affect the image tools, but I guess
89 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
90 .ascii CONFIG_IDENT_STRING, "\0"
93 * Hard Reset Configuration Word (HRCW) table
95 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
96 * such as whether there is an external memory controller, whether the
97 * PowerPC core is disabled (i.e. only the communications processor is
98 * active, accessed by another CPU on the bus), whether using external
99 * arbitration, external bus mode, boot port size, core initial prefix,
100 * internal space base, boot memory space, etc.
102 * These things dictate where the processor begins execution, where the
103 * boot ROM appears in memory, the memory controller setup when access
104 * boot ROM, etc. The HRCW is *extremely* important.
106 * The HRCW is read from the bus during reset. One CPU on the bus will
107 * be a hard reset configuration master, any others will be hard reset
108 * configuration slaves. The master reads eight HRCWs from flash during
109 * reset - the first it uses for itself, the other 7 it communicates to
110 * up to 7 configuration slaves by some complicated mechanism, which is
111 * not really important here.
113 * The configuration master performs 32 successive reads starting at address
114 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
115 * bits is read, and always from byte lane D[0-7] (so that port size of the
116 * boot device does not matter). The first four reads form the 32 bit HRCW
117 * for the master itself. The second four reads form the HRCW for the first
118 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
119 * concatenating the four bytes, with the first read placed in byte 0 (the
120 * most significant byte), and so on with the fourth read placed in byte 3
121 * (the least significant byte).
123 #define _HRCW_TABLE_ENTRY(w) \
124 .fill 8,1,(((w)>>24)&0xff); \
125 .fill 8,1,(((w)>>16)&0xff); \
126 .fill 8,1,(((w)>> 8)&0xff); \
127 .fill 8,1,(((w) )&0xff)
131 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
132 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
133 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
134 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
135 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
136 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
137 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
138 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
140 * After configuration, a system reset exception is executed using the
141 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
142 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
143 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
144 * of MSR[IP] is determined by the CIP field in the HRCW.
146 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
147 * This determines the location of the boot ROM (flash or EPROM) in the
148 * processor's address space at boot time. As long as the HRCW is set up
149 * so that we eventually end up executing the code below when the processor
150 * executes the reset exception, the actual values used should not matter.
152 * Once we have got here, the address mask in OR0 is cleared so that the
153 * bottom 32K of the boot ROM is effectively repeated all throughout the
154 * processor's address space, after which we can jump to the absolute
155 * address at which the boot ROM was linked at compile time, and proceed
156 * to initialise the memory controller without worrying if the rug will be
157 * pulled out from under us, so to speak (it will be fine as long as we
158 * configure BR0 with the same boot ROM link address).
160 . = EXC_OFF_SYS_RESET
164 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
168 . = EXC_OFF_SYS_RESET + 0x10
172 li r21, BOOTFLAG_WARM /* Software reboot */
176 #if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
177 lis r3, CONFIG_SYS_DEFAULT_IMMR@h
181 rlwinm r4, r4, 0, 8, 5
187 #endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
189 mfmsr r5 /* save msr contents */
191 #if defined(CONFIG_COGENT)
192 /* this is what the cogent EPROM does */
197 #endif /* CONFIG_COGENT */
199 #if defined(CONFIG_SYS_DEFAULT_IMMR)
200 lis r3, CONFIG_SYS_IMMR@h
201 ori r3, r3, CONFIG_SYS_IMMR@l
202 lis r4, CONFIG_SYS_DEFAULT_IMMR@h
204 #endif /* CONFIG_SYS_DEFAULT_IMMR */
206 /* Initialise the MPC8260 processor core */
207 /*--------------------------------------------------------------*/
211 #ifndef CONFIG_SYS_RAMBOOT
212 /* When booting from ROM (Flash or EPROM), clear the */
213 /* Address Mask in OR0 so ROM appears everywhere */
214 /*--------------------------------------------------------------*/
216 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
222 /* Calculate absolute address in FLASH and jump there */
223 /*--------------------------------------------------------------*/
225 lis r3, CONFIG_SYS_MONITOR_BASE@h
226 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
227 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
232 #endif /* CONFIG_SYS_RAMBOOT */
234 /* initialize some things that are hard to access from C */
235 /*--------------------------------------------------------------*/
237 lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
238 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
239 li r0, 0 /* Make room for stack frame header and */
240 stwu r0, -4(r1) /* clear final stack frame so that */
241 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
243 /* let the C-code set up the rest */
245 /* Be careful to keep code relocatable ! */
246 /*--------------------------------------------------------------*/
248 GET_GOT /* initialize GOT access */
251 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
254 bl init_debug /* set up debugging stuff */
259 bl board_init_f /* run 1st part of board init code (in Flash)*/
265 .globl _start_of_vectors
269 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
271 /* Data Storage exception. */
272 STD_EXCEPTION(0x300, DataStorage, UnknownException)
274 /* Instruction Storage exception. */
275 STD_EXCEPTION(0x400, InstStorage, UnknownException)
277 /* External Interrupt exception. */
278 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
280 /* Alignment exception. */
283 EXCEPTION_PROLOG(SRR0, SRR1)
288 addi r3,r1,STACK_FRAME_OVERHEAD
290 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
291 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
292 lwz r6,GOT(transfer_to_handler)
296 .long AlignmentException - _start + EXC_OFF_SYS_RESET
297 .long int_return - _start + EXC_OFF_SYS_RESET
299 /* Program check exception */
302 EXCEPTION_PROLOG(SRR0, SRR1)
303 addi r3,r1,STACK_FRAME_OVERHEAD
305 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
306 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
307 lwz r6,GOT(transfer_to_handler)
311 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
312 .long int_return - _start + EXC_OFF_SYS_RESET
314 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
316 /* I guess we could implement decrementer, and may have
317 * to someday for timekeeping.
319 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
321 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
322 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
323 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
324 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
326 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
327 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
329 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
330 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
331 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
335 * This exception occurs when the program counter matches the
336 * Instruction Address Breakpoint Register (IABR).
338 * I want the cpu to halt if this occurs so I can hunt around
339 * with the debugger and look at things.
341 * When DEBUG is defined, both machine check enable (in the MSR)
342 * and checkstop reset enable (in the reset mode register) are
343 * turned off and so a checkstop condition will result in the cpu
346 * I force the cpu into a checkstop condition by putting an illegal
347 * instruction here (at least this is the theory).
349 * well - that didnt work, so just do an infinite loop!
353 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
355 STD_EXCEPTION(0x1400, SMI, UnknownException)
357 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
358 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
359 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
360 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
361 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
362 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
363 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
364 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
365 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
366 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
367 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
368 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
369 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
370 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
371 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
372 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
373 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
374 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
375 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
376 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
377 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
378 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
379 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
380 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
381 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
382 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
383 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
386 .globl _end_of_vectors
392 * This code finishes saving the registers to the exception frame
393 * and jumps to the appropriate handler for the exception.
394 * Register r21 is pointer into trap frame, r1 has new stack pointer.
396 .globl transfer_to_handler
407 andi. r24,r23,0x3f00 /* get vector offset */
411 lwz r24,0(r23) /* virtual address of handler */
412 lwz r23,4(r23) /* where to go when done */
417 rfi /* jump to handler, enable MMU */
420 mfmsr r28 /* Disable interrupts */
424 SYNC /* Some chip revs need this... */
439 lwz r2,_NIP(r1) /* Restore environment */
449 #if defined(CONFIG_COGENT)
452 * This code initialises the MPC8260 processor core
453 * (conforms to PowerPC 603e spec)
456 .globl cogent_init_8260
459 /* Taken from page 14 of CMA282 manual */
460 /*--------------------------------------------------------------*/
462 lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
463 lis r3, CONFIG_SYS_IMMR@h
464 stw r3, IM_IMMR@l(r4)
465 lwz r3, IM_IMMR@l(r4)
467 lis r3, CONFIG_SYS_SYPCR@h
468 ori r3, r3, CONFIG_SYS_SYPCR@l
469 stw r3, IM_SYPCR@l(r4)
470 lwz r3, IM_SYPCR@l(r4)
472 lis r3, CONFIG_SYS_SCCR@h
473 ori r3, r3, CONFIG_SYS_SCCR@l
474 stw r3, IM_SCCR@l(r4)
475 lwz r3, IM_SCCR@l(r4)
478 /* the rest of this was disassembled from the */
479 /* EPROM code that came with my CMA282 CPU module */
480 /*--------------------------------------------------------------*/
494 /*--------------------------------------------------------------*/
498 #endif /* CONFIG_COGENT */
501 * This code initialises the MPC8260 processor core
502 * (conforms to PowerPC 603e spec)
503 * Note: expects original MSR contents to be in r5.
506 .globl init_8260_core
509 /* Initialize machine status; enable machine check interrupt */
510 /*--------------------------------------------------------------*/
512 li r3, MSR_KERNEL /* Set ME and RI flags */
513 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
515 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
517 SYNC /* Some chip revs need this... */
520 mtspr SRR1, r3 /* Make SRR1 match MSR */
522 /* Initialise the SYPCR early, and reset the watchdog (if req) */
523 /*--------------------------------------------------------------*/
525 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
526 #if !defined(CONFIG_COGENT)
527 lis r4, CONFIG_SYS_SYPCR@h
528 ori r4, r4, CONFIG_SYS_SYPCR@l
529 stw r4, IM_SYPCR@l(r3)
530 #endif /* !CONFIG_COGENT */
531 #if defined(CONFIG_WATCHDOG)
532 li r4, 21868 /* = 0x556c */
533 sth r4, IM_SWSR@l(r3)
534 li r4, -21959 /* = 0xaa39 */
535 sth r4, IM_SWSR@l(r3)
536 #endif /* CONFIG_WATCHDOG */
538 /* Initialize the Hardware Implementation-dependent Registers */
539 /* HID0 also contains cache control */
540 /*--------------------------------------------------------------*/
542 lis r3, CONFIG_SYS_HID0_INIT@h
543 ori r3, r3, CONFIG_SYS_HID0_INIT@l
547 lis r3, CONFIG_SYS_HID0_FINAL@h
548 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
552 lis r3, CONFIG_SYS_HID2@h
553 ori r3, r3, CONFIG_SYS_HID2@l
556 /* clear all BAT's */
557 /*--------------------------------------------------------------*/
578 /* invalidate all tlb's */
580 /* From the 603e User Manual: "The 603e provides the ability to */
581 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
582 /* instruction invalidates the TLB entry indexed by the EA, and */
583 /* operates on both the instruction and data TLBs simultaneously*/
584 /* invalidating four TLB entries (both sets in each TLB). The */
585 /* index corresponds to bits 15-19 of the EA. To invalidate all */
586 /* entries within both TLBs, 32 tlbie instructions should be */
587 /* issued, incrementing this field by one each time." */
589 /* "Note that the tlbia instruction is not implemented on the */
592 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
593 /* incrementing by 0x1000 each time. The code below is sort of */
594 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
596 /*--------------------------------------------------------------*/
607 /*--------------------------------------------------------------*/
614 * initialise things related to debugging.
616 * must be called after the global offset table (GOT) is initialised
617 * (GET_GOT) and after cpu_init_f() has executed.
623 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
625 /* Quick and dirty hack to enable the RAM and copy the */
626 /* vectors so that we can take exceptions. */
627 /*--------------------------------------------------------------*/
628 /* write Memory Refresh Prescaler */
629 li r4, CONFIG_SYS_MPTPR
630 sth r4, IM_MPTPR@l(r3)
631 /* write 60x Refresh Timer */
632 li r4, CONFIG_SYS_PSRT
633 stb r4, IM_PSRT@l(r3)
634 /* init the 60x SDRAM Mode Register */
635 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
636 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
637 stw r4, IM_PSDMR@l(r3)
638 /* write Precharge All Banks command */
639 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
640 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
641 stw r4, IM_PSDMR@l(r3)
643 /* write eight CBR Refresh commands */
644 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
645 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
646 stw r4, IM_PSDMR@l(r3)
655 /* write Mode Register Write command */
656 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
657 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
658 stw r4, IM_PSDMR@l(r3)
660 /* write Normal Operation command and enable Refresh */
661 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
662 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
663 stw r4, IM_PSDMR@l(r3)
665 /* RAM should now be operational */
667 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
669 lwz r3, GOT(_end_of_vectors)
670 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
671 lis r5, VEC_WRD_CNT@h
672 ori r5, r5, VEC_WRD_CNT@l
679 /* Load the Instruction Address Breakpoint Register (IABR). */
681 /* The address to load is stored in the first word of dual port */
682 /* ram and should be preserved while the power is on, so you */
683 /* can plug addresses into that location then reset the cpu and */
684 /* this code will load that address into the IABR after the */
687 /* When the program counter matches the contents of the IABR, */
688 /* an exception is generated (before the instruction at that */
689 /* location completes). The vector for this exception is 0x1300 */
690 /*--------------------------------------------------------------*/
691 lis r3, CONFIG_SYS_IMMR@h
695 /* Set the entire dual port RAM (where the initial stack */
696 /* resides) to a known value - makes it easier to see where */
697 /* the stack has been written */
698 /*--------------------------------------------------------------*/
699 lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
700 ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
701 li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
704 ori r4, r4, 0xdeadbeaf@l
710 /*--------------------------------------------------------------*/
717 * Note: requires that all cache bits in
718 * HID0 are in the low half word.
725 ori r4, r4, HID0_ILOCK
727 ori r4, r3, HID0_ICFI
729 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
731 mtspr HID0, r3 /* clears invalidate */
734 .globl icache_disable
738 ori r4, r4, HID0_ICE|HID0_ILOCK
740 ori r4, r3, HID0_ICFI
742 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
744 mtspr HID0, r3 /* clears invalidate */
750 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
758 ori r4, r4, HID0_DLOCK
762 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
764 mtspr HID0, r3 /* clears invalidate */
767 .globl dcache_disable
771 ori r4, r4, HID0_DCE|HID0_DLOCK
775 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
777 mtspr HID0, r3 /* clears invalidate */
783 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
791 /*------------------------------------------------------------------------------*/
794 * void relocate_code (addr_sp, gd, addr_moni)
796 * This "function" does not return, instead it continues in RAM
797 * after relocating the monitor code.
801 * r5 = length in bytes
806 mr r1, r3 /* Set new stack pointer */
807 mr r9, r4 /* Save copy of Global Data pointer */
808 mr r10, r5 /* Save copy of Destination Address */
810 mr r3, r5 /* Destination Address */
811 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
812 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
813 lwz r5, GOT(__init_end)
815 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
820 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
826 /* First our own GOT */
828 /* then the one used by the C code */
838 beq cr1,4f /* In place copy is not necessary */
839 beq 7f /* Protect against 0 count */
858 * Now flush the cache: note that we must start from a cache aligned
859 * address. Otherwise we might miss one cache line.
863 beq 7f /* Always flush prefetch queue in any case */
866 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
867 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
875 sync /* Wait for all dcbst to complete on bus */
876 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
877 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
885 7: sync /* Wait for all icbi to complete on bus */
889 * We are done. Do not return, instead branch to second part of board
890 * initialization, now running from RAM.
893 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
900 * Relocation Function, r14 point to got2+0x8000
902 * Adjust got2 pointers, no need to check for 0, this code
903 * already puts a few entries in the table.
905 li r0,__got2_entries@sectoff@l
906 la r3,GOT(_GOT2_TABLE_)
907 lwz r11,GOT(_GOT2_TABLE_)
917 * Now adjust the fixups and the pointers to the fixups
918 * in case we need to move ourselves again.
920 2: li r0,__fixup_entries@sectoff@l
921 lwz r3,GOT(_FIXUP_TABLE_)
935 * Now clear BSS segment
937 lwz r3,GOT(__bss_start)
938 #if defined(CONFIG_HYMOD)
940 * For HYMOD - the environment is the very last item in flash.
941 * The real .bss stops just before environment starts, so only
942 * clear up to that point.
944 * taken from mods for FADS board
946 lwz r4,GOT(environment)
962 mr r3, r9 /* Global Data pointer */
963 mr r4, r10 /* Destination Address */
967 * Copy exception vector code to low memory
970 * r7: source address, r8: end address, r9: target address
975 lwz r8, GOT(_end_of_vectors)
977 li r9, 0x100 /* reset vector always at 0x100 */
980 bgelr /* return if r7>=r8 - just in case */
982 mflr r4 /* save link register */
992 * relocate `hdlr' and `int_return' entries
994 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
995 li r8, Alignment - _start + EXC_OFF_SYS_RESET
998 addi r7, r7, 0x100 /* next exception vector */
1002 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1005 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1008 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1009 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1012 addi r7, r7, 0x100 /* next exception vector */
1016 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1017 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1020 addi r7, r7, 0x100 /* next exception vector */
1024 mfmsr r3 /* now that the vectors have */
1025 lis r7, MSR_IP@h /* relocated into low memory */
1026 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1027 andc r3, r3, r7 /* (if it was on) */
1028 SYNC /* Some chip revs need this... */
1032 mtlr r4 /* restore link register */
1036 * Function: relocate entries for one exception vector
1039 lwz r0, 0(r7) /* hdlr ... */
1040 add r0, r0, r3 /* ... += dest_addr */
1043 lwz r0, 4(r7) /* int_return ... */
1044 add r0, r0, r3 /* ... += dest_addr */