3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/m8260_pci.h>
33 * Local->PCI map (from CPU) controlled by
34 * MPC826x master window
36 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
37 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
39 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
40 * PCI Mem with prefetch
42 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
43 * PCI Mem w/o prefetch
45 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
48 * PCI->Local map (from PCI)
49 * MPC826x slave window controlled by
51 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
52 * MPC826x local memory
56 * Slave window that allows PCI masters to access MPC826x local memory.
57 * This window is set up using the first set of Inbound ATU registers
60 #ifndef CFG_PCI_SLV_MEM_LOCAL
61 #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
63 #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
66 #ifndef CFG_PCI_SLV_MEM_BUS
67 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
69 #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
72 #ifndef CFG_PICMR0_MASK_ATTRIB
73 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
76 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
80 * These are the windows that allow the CPU to access PCI address space.
81 * All three PCI master windows, which allow the CPU to access PCI
82 * prefetch, non prefetch, and IO space (see below), must all fit within
87 #ifndef CFG_PCI_MSTR0_LOCAL
88 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
90 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
93 #ifndef CFG_PCIMSK0_MASK
94 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
96 #define PCIMSK0_MASK CFG_PCIMSK0_MASK
100 #ifndef CFG_PCI_MSTR1_LOCAL
101 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
103 #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
106 #ifndef CFG_PCIMSK1_MASK
107 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
109 #define PCIMSK1_MASK CFG_PCIMSK1_MASK
113 * Master window that allows the CPU to access PCI Memory (prefetch).
114 * This window will be setup with the first set of Outbound ATU registers
118 #ifndef CFG_PCI_MSTR_MEM_LOCAL
119 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
121 #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
124 #ifndef CFG_PCI_MSTR_MEM_BUS
125 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
127 #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
130 #ifndef CFG_CPU_PCI_MEM_START
131 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
133 #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
136 #ifndef CFG_PCI_MSTR_MEM_SIZE
137 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
139 #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
142 #ifndef CFG_POCMR0_MASK_ATTRIB
143 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
145 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
149 * Master window that allows the CPU to access PCI Memory (non-prefetch).
150 * This window will be setup with the second set of Outbound ATU registers
154 #ifndef CFG_PCI_MSTR_MEMIO_LOCAL
155 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
157 #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
160 #ifndef CFG_PCI_MSTR_MEMIO_BUS
161 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
163 #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
166 #ifndef CFG_CPU_PCI_MEMIO_START
167 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
169 #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
172 #ifndef CFG_PCI_MSTR_MEMIO_SIZE
173 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
175 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
178 #ifndef CFG_POCMR1_MASK_ATTRIB
179 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
181 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
185 * Master window that allows the CPU to access PCI IO space.
186 * This window will be setup with the third set of Outbound ATU registers
190 #ifndef CFG_PCI_MSTR_IO_LOCAL
191 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
193 #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
196 #ifndef CFG_PCI_MSTR_IO_BUS
197 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
199 #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
202 #ifndef CFG_CPU_PCI_IO_START
203 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
205 #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
208 #ifndef CFG_PCI_MSTR_IO_SIZE
209 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
211 #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
214 #ifndef CFG_POCMR2_MASK_ATTRIB
215 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
217 #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
220 /* PCI bus configuration registers.
223 #define PCI_CLASS_BRIDGE_CTLR 0x06
226 static inline void pci_outl (u32 addr, u32 data)
228 *(volatile u32 *) addr = cpu_to_le32 (data);
231 void pci_mpc8250_init (struct pci_controller *hose)
233 #ifdef CONFIG_MPC8266ADS
234 DECLARE_GLOBAL_DATA_PTR;
238 volatile immap_t *immap = (immap_t *) CFG_IMMR;
239 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
241 pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
242 CFG_IMMR + PCI_CFG_DATA_REG);
245 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
247 #ifdef CONFIG_MPC8266ADS
248 immap->im_siu_conf.sc_siumcr =
249 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
253 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
254 * and local bus for PCI (SIUMCR [LBPC]).
256 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
265 /* Make PCI lowest priority */
266 /* Each 4 bits is a device bus request and the MS 4bits
267 is highest priority */
277 External Master 1 0b0111
278 External Master 2 0b1000
279 External Master 3 0b1001
280 The rest are reserved */
281 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
283 /* Park bus on core while modifying PCI Bus accesses */
284 immap->im_siu_conf.sc_ppc_acr = 0x6;
287 * Set up master windows that allow the CPU to access PCI space. These
288 * windows are set up using the two SIU PCIBR registers.
290 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
291 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
293 #ifdef CONFIG_MPC8266ADS
294 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
295 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
298 /* Release PCI RST (by default the PCI RST signal is held low) */
299 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
301 /* give it some time */
303 #ifdef CONFIG_MPC8266ADS
304 /* Give the PCI cards more time to initialize before query
305 This might be good for other boards also
309 for (i = 0; i < 1000; ++i)
315 * Set up master window that allows the CPU to access PCI Memory (prefetch)
316 * space. This window is set up using the first set of Outbound ATU registers.
318 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
319 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
320 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
323 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
324 * space. This window is set up using the second set of Outbound ATU registers.
326 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
327 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
328 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
331 * Set up master window that allows the CPU to access PCI IO space. This window
332 * is set up using the third set of Outbound ATU registers.
334 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
335 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
336 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
339 * Set up slave window that allows PCI masters to access MPC826x local memory.
340 * This window is set up using the first set of Inbound ATU registers
342 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
343 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
344 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
346 /* See above for description - puts PCI request as highest priority */
347 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
349 /* Park the bus on the PCI */
350 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
352 /* Host mode - specify the bridge as a host-PCI bridge */
354 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
355 PCI_CLASS_BRIDGE_CTLR);
357 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
358 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
359 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
360 tempShort | PCI_COMMAND_MASTER |
363 /* do some bridge init, should be done on all 8260 based bridges */
364 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
366 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
369 hose->first_busno = 0;
370 hose->last_busno = 0xff;
372 /* System memory space */
373 #ifdef CONFIG_MPC8266ADS
374 pci_set_region (hose->regions + 0,
377 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
379 pci_set_region (hose->regions + 0,
382 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
385 /* PCI memory space */
386 #ifdef CONFIG_MPC8266ADS
387 pci_set_region (hose->regions + 1,
389 PCI_MSTR_MEMIO_LOCAL,
390 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
392 pci_set_region (hose->regions + 1,
395 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
399 pci_set_region (hose->regions + 2,
401 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
403 hose->region_count = 3;
405 pci_register_hose (hose);
406 /* Mask off master abort machine checks */
407 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
410 hose->last_busno = pci_hose_scan (hose);
413 /* clear the error in the error status register */
414 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
416 /* unmask master abort machine checks */
417 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
420 #endif /* CONFIG_PCI */